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# Hardware/Software Codesign and Performance Engineer, Inference

- **Company:** Google LLC
- **Location:** Sunnyvale, CA, United States
- **Salary:** $240,000.0 - $333,000.0
- **Contract:** Permanent contract
- **Skills:** Computer Engineering, Systems Analysis, Machine Learning, Performance Tuning, Tensorflow, Pytorch, Deep Learning, Information Technology, Machine Learning Operations
- **Published:** October 28, 2026
- **Apply:** https://dejobs.org/x/x/497661BA3B48468AB46CDB4768B6453C/job/

## About the Role

Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders; deep expertise in domain.

Share Hardware/Software Codesign and Performance Engineer, Inference, * Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

 * 12 years of experience in computer architecture, chip architecture, or hardware-software co-design.
 * Experience developing systems for performance modeling, simulation, or system analysis., * Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
 * Experience as a lead architect driving multi-generational hardware solutions or performance optimizations for massive-scale ML training and inference.
 * Experience with deep learning frameworks (e.g., PyTorch, TensorFlow) and their underlying execution models.
 * Knowledge of semiconductor trajectories, including process, memory, interconnects, and packaging.
 * Understanding of ML trends, business drivers, and the software ecosystem.
 * Ability to engage and align stakeholders, hardware designers, and the global ML research community.

## Description

* Define and drive the technical roadmap and architecture for the hardware/software stack, ensuring unparalleled performance for the training and serving of large ML models.
 * Act as the technical liaison between advanced research, software, and hardware teams, steering model architecture innovation to maximize scaling, quality, and hardware efficiency.
 * Architect and oversee the development of next-generation configurable simulation frameworks and cycle-accurate performance models, setting the standard for how the organization evaluates complex micro-architectural decisions.
 * Advocate system-level performance analysis across highly distributed ML systems, innovating new methodologies to balance compute, memory bandwidth, and inter-chip network requirements.
 * Manage cross-functional partnerships across hardware engineering, compiler development, and ML research to influence broad organizational strategy and transition paradigm-shifting concepts into production.