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# Senior FPGA SoC Engineer

- **Company:** Think Consulting
- **Location:** Chandler, AZ, United States
- **Experience:** Expert
- **Salary:** $150,000.0 - $180,000.0
- **Contract:** Permanent contract
- **Skills:** C (Programming Language), Microsoft Word, Microsoft Excel, Gigabit Ethernet, Address Resolution Protocols, C++ (Programming Language), Computer Engineering, Software Debugging, Logic Synthesis of Circuits, Linux on Embedded Systems, Embedded Software, Ethernet, Firmware, Field-Programmable Gate Array (FPGA), Internet Control Message Protocol, Internet Group Management Protocols, IPv4, IPv6, Network Security, Microsoft Visio, Network Protocols, PCI Express, Microsoft PowerPoint, Zero Trust Network Access, Schematic Capture, Static Timing Analysis, System on a Chip, SystemVerilog, Systems Integration, Transmission Control Protocol (TCP), VHSIC Hardware Description Language (VHDL), IEEE 802.3, Vivado, Application Specific Integrated Circuits, Fpga Hardware, Git, Yocto, Evolved Common Public Radio Interface (eCPRI), Pcb Layout, U-Boot, Cisco
- **Published:** October 30, 2026
- **Apply:** https://diversityjobs.com/career/18778501/Senior-Fpga-Soc-Engineer-Arizona-Chandler

## About the Role

* Deep digital design skills with hands-on FPGA or ASIC SoC experience
 * Strong implementation experience in Client/Altera Quartus or AMD/Xilinx Vivado
 * Experience designing and debugging SoC systems built around AMBA AXI and APB interfaces
 * A track record of building high-throughput, pipelined AXI-Stream IP optimized for maximum clock frequency
 * Ability to build RTL simulations that catch and resolve most issues before testing on hardware
 * Working knowledge of static timing analysis and SDC constraints, including reading STA reports and examining post-synthesis netlists and placement to fix failing paths
 * Experience contributing to schematic capture and PCB layout for the FPGA portions of a board
 * Implementation experience with at least one high-speed serial protocol, such as PCI Express, Interlaken, USB SuperSpeed, 1000BASE-X/SGMII, 10GBASE-R, 40GBASE-R4, or 100GBASE-R4
 * Experience implementing network protocols across the stack:
 + Layer 1: IEEE 802.3 Ethernet (1G to 100G), including Cisco and SFP/QSFP MSA standards
 + Layers 2/3: IPv4, IPv6, ARP, ICMP, IGMP, UDP, TCP
 + Upper layer, strongly preferred: VITA 49.2, IEEE-ISTO 4900 (DIFI), and/or eCPRI
 * Proficiency in C, C++, and Git
 * Proficiency with standard office and diagramming tools (Word, Excel, PowerPoint, Visio)
 * Experience supporting multi-disciplinary, cross-functional, matrixed teams

Nice to Have

 * Working knowledge of digital IF streaming standards such as VITA 49.2, DIFI, or eCPRI ( strongly preferred)
 * Familiarity with embedded Linux: kernel, Yocto, U-Boot, and device tree
 * Familiarity with satellite waveforms such as DVB-S2X and/or 5G NTN (3GPP Release 17/18)
 * Understanding of network security in zero-trust environments
 * Experience with partial reconfiguration (DFX) or PCIe CvP
 * Active DoD clearance, or ability to obtain one

Education & Experience

 * Bachelor's degree in electrical or computer engineering, or a related field
 * 5+ years of FPGA or ASIC SoC design experience

## Description

You will take technical ownership of complex FPGA SoC designs for satellite communication platforms. The work covers the full design flow: integrating third-party and in-house IP, writing high-performance RTL, and developing the userspace drivers and embedded firmware that make the hardware usable. You will design, build, debug, and verify these systems end to end, working closely with teammates and engineering management.

What You'll Do

 * Design, implement, document, debug, and test FPGA SoC systems, including:
 + Integrating IP into FPGA projects through synthesis and implementation
 + Developing high-performance FPGA IP in VHDL and SystemVerilog
 + Writing userspace drivers for FPGA IP in C++
 + Writing firmware for embedded microcontrollers in C
 * Communicate clearly and collaborate effectively with peers and engineering leadership