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# Sr. ASIC DFT Engineer (Silicon)

- **Company:** Space Exploration Technologies Corp.
- **Location:** Irvine, CA, United States
- **Experience:** Expert
- **Salary:** $165,000.0 - $260,000.0
- **Contract:** Permanent contract
- **Skills:** Data Analysis, C++ (Programming Language), Computer Engineering, Software Debugging, Perl (Programming Language), Python (Programming Language), Data Streaming, Subsystems, System Testing, Tcl (Programming Language), Application Specific Integrated Circuits, Test Scripts, Yield Optimization, Programming Languages
- **Published:** October 30, 2026
- **Apply:** https://www.adzuna.com/details/5748340094

## About the Role

* Bachelor's degree in electrical engineering, computer engineering, or physics
 * 5+ years of experience in semiconductor Design For Test (DFT) engineering, post-silicon validation, and/or production testing, * Master's or PhD in electrical engineering, computer engineering, physics, or related engineering field
 * Extensive experience in post-silicon bringup, including silicon debug, failure analysis, and yield optimization on complex SoCs or ASICs
 * Hands-on experience with Automated Test Equipment (ATE) platforms (e.g., Teradyne, Advantest) for high-volume manufacturing test development and debug
 * Experience collaborating with cross-functional teams (e.g., design, verification, and manufacturing) to ensure DFT features meet production requirements, utilizing Siemens Tessent workflows
 * Knowledge of industry standards for testability (e.g., IEEE 1500, 1687) and experience with low-power DFT techniques using Siemens Tessent
 * Experience with In-System Test (IST), boundary scan (IEEE 1149.1), functional testing in embedded systems, or board-level diagnostics, preferably using Siemens Tessent tools
 * Hands-on experience with Tessent Streaming Scan Network
 * Experience with cell-aware fault models in ATPG
 * Excellent problem-solving skills, with the ability to analyze complex test failures and implement corrective actions
 * Strong communication skills for documenting test strategies, reporting results, and presenting to stakeholders
 * Ability to work in a fast-paced environment, handling multiple projects and adapting to evolving technology nodes (e.g., 7nm and below)

ADDITIONAL REQUIREMENTS:

 * Ability to work extended hours and weekends as needed to meet critical milestones

## Description

* Implement and optimize DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools
 * Integration and verification of Design for Test (DFT) IPs and fabrics within Subsystems
 * Set up and run Automatic Test Pattern Generation (ATPG) tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows.
 * Run and debug non-timing and SDF annotated gate-level simulations
 * Create and validate DFT patterns for post-silicon bringup and also help with ATE debug through all cycles of silicon characterization
 * Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl, or C++