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# Design Engineer 7848

- **Company:** Taiwan Semiconductor Manufacturing Co Ltd
- **Location:** Los Angeles, CA, United States
- **Salary:** $155,896 - $156,000
- **Contract:** Permanent contract
- **Skills:** Computer Programming, Computer Engineering, Logic Synthesis of Circuits, Electronic Design Automation, Perl (Programming Language), Hardware Design, Tcl (Programming Language), Linux Virtual Server, Vlsi Design, Physical Verification, Physical Design
- **Published:** October 30, 2026
- **Apply:** https://www.careerbuilder.com/job-details/design-engineer-7848-los-angeles-ca--01ea22a3-f5d7-442b-8051-b2a18ce68ccf

## About the Role

Technical/Engineering Design, Technical/Engineering Design, Antenna, Analysis Skills, Place and Route, Timing Verification, Noise Analysis, Schematics, eCos, LVS Flows, Requirements: Master's degree or foreign equivalent in Electrical Engineering, Computer Engineering, or a related field of study.

Work experience or academic coursework must have included: Experience in RTL coding, digital design and testing, physical implementation or design verification; Experience in Perl/TCL language programming; Experience with N16 and below technology; Experience with Chip level integration, and wire editing, Low-power implementation methodology; Experience with Netlist-GDS P&R, signoff task; Experience in block level implementation or chip integration and signoff; Knowledge of major EDA tools/design flows; and knowledge of hardware design including VLSI design, digital integrated circuits, logic design, design for testing, computer architecture, and digital design automation.

## Description

Job Descriptions: Responsible for the Design Rule Check, Layout vs. Schematic checking and fixing all PDV/EMIR/Noise/SigEM violations and errors. You may also do customization and implementation of top clocks and implement timing ECOs on high performance blocks. Specific job duties include: DRC/LVS/ERC/ANTENNA analysis and clean up, Floorplan analysis and congestion solution; Power IR/EM analysis and fix; Signal EM/Noise analysis and fix; Physical verification sign off; Implement ECOs for timing closure; Customized Clock tree structure; May also perform floorplan, place and route.