> Markdown version of [/jobs/ext/4034808-principal-firmware-engineer-power-conversion-control](https://www.wearedevelopers.com/jobs/ext/4034808-principal-firmware-engineer-power-conversion-control). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Principal Firmware Engineer - Power Conversion Control - **Company:** ZAPBATT, INC. - **Location:** Carlsbad, CA, United States - **Experience:** Expert - **Salary:** $165,000.0 - $205,000.0 - **Contract:** Permanent contract - **Skills:** Abstraction Layers, Aliasing, ARM Architecture, Unit Testing, CANopen, Network Analysis, Static Program Analysis, Code Review, Computer Engineering, Software Debugging, Embedded Software, Firmware, Failure Mode Effects Analysis, Hardware Design, Hardware-In-The-Loop Simulation, LTspice, MATLAB, MISRA C (C Programming Language), Software Safety, Requirements Traceability, Digital Access Carrier System, PIC Microcontroller, Real Time Systems, Modeling and Simulation, Ripple (payment Protocol), Software Version Control - **Published:** October 30, 2026 - **Apply:** https://www.careerbuilder.com/job-details/principal-firmware-engineer-power-conversion-control-carlsbad-ca--01a701f2-bd11-42ce-987e-6e67ea3d60cb ## About the Role Computer Firmware, Power Engineering, Computer Firmware, Embedded Systems, Budgeting, Microcontroller, Topology, Schedule Development, Model Verification, Comparator, * BS in Electrical Engineering, Computer Engineering, or equivalent demonstrated capability. * Six or more years developing production embedded firmware in C for resource-constrained real-time systems. * Direct, hands-on experience closing control loops in firmware on switched-mode power converters. You can name the topology, control mode, switching and sampling frequencies, compensator structure, and achieved crossover and phase margin for a converter you personally brought to validated hardware. * Working command of discrete-time control: s-to-z mapping (bilinear/Tustin, zero-order hold), the effect of sampling and computational delay on phase margin, aliasing, and quantization. * Fluency with the peripherals that make digital power work: high-resolution PWM, PWM-triggered ADC with programmable sample instants, analog comparators and DACs for fast fault paths, and DMA. * Fixed-point arithmetic competence - Q-format scaling, range and overflow analysis, saturating behavior - and the ability to justify a fixed-point versus floating-point decision on execution-time grounds. * Deterministic ISR design under hard timing constraints, including the ability to measure and defend worst-case execution time rather than estimate it. * Independent lab capability with oscilloscopes, isolated and differential probes, current probes, electronic loads, bidirectional supplies, and a network or frequency response analyzer for loop gain measurement. * Version control, code review, and a demonstrated track record of writing specifications and test evidence, not only, * dsPIC experience (significant advantage) * Production firmware on dsPIC33C, dsPIC33CK, or dsPIC33CH digital signal controllers for power conversion, including high-resolution PWM generators with PCI-based synchronization, dedicated and shared ADC core configuration, early interrupt generation, alternate working register sets, DSP MAC instruction use in compensator inner loops, and MPLAB X / XC16 toolchain depth. * Familiarity with Microchip's digital power reference ecosystem - Digital Power Development Board, Digital Power Plug-In Modules, and the PowerSmart Digital Control Library Designer. Additional preferred experience * Bidirectional and multiphase interleaved converter control, including current sharing and phase balancing between paralleled phases. * Average current mode control implementation specifically, as distinct from voltage mode or peak current mode. * Wide-bandgap power stages (GaN, SiC) and the firmware-visible consequences of fast switching edges - sense chain noise, blanking, dead-time sensitivity, and gate-drive fault behavior. * ARM Cortex-M devices with advanced timer peripherals in addition to dsPIC; we value portability across both architectures. * Battery energy storage, EV charging, photovoltaic inverter, or grid-interactive converter experience, including charge profile management and BMS interaction such as current limit negotiation, precharge, and contactor sequencing. * Functional safety and certification exposure: IEC 61508 or ISO 26262 concepts, UL 1973, UL 1998, UL 9540, FMEA/FMEDA, and software safety requirements traceability. * MISRA C, static analysis, on-target unit testing, and hardware- or processor-in-the-loop infrastructure. * Modeling and simulation in SPICE/LTspice, PLECS, or MATLAB/Simulink, with the ability to build the model rather than only run an existing one. * CAN and CANopen, and firmware update over an embedded bus. * Contributions to reusable, portable control libraries with clean hardware abstraction, as opposed to one-off application firmware. ## Description Proper Voltage designs and builds safety-critical battery energy storage systems. This role owns the real-time control firmware for our bidirectional DC/DC power conversion stage - the code that closes current and voltage loops on multiphase interleaved converters, arbitrates operating modes, and commands a safe state when a fault occurs. This is not a general embedded role that happens to touch PWM. You will be fluent in both the control theory and the silicon: able to derive a plant model and a discrete-time compensator, implement it within a sub-microsecond ISR budget with correct fixed-point scaling and correct ADC-to-PWM trigger phasing, then measure the resulting loop gain on the bench and explain why it does or does not match the model. You will own our portable, MCU-agnostic DC/DC control library and its normative specifications, and become the primary technical authority on converter control firmware within the organization. What you'll do * Real-time control loop implementation for four-switch buck-boost power stages and successor topologies, including multiphase interleaved operation and phase current balancing. * The portable DC/DC control library: compensator implementations, mode arbitration, scheduler and ISR architecture, and the platform abstraction layer. * Converter protection firmware - cycle-by-cycle current limit, overvoltage and undervoltage, thermal derating, gate-drive fault handling, and safe-state transitions. * Control loop verification: model-to-measurement correlation, loop gain and stability margin characterization, transient response, and stability across the full operating envelope. * Normative control specifications and the traceable verification evidence supporting UL 1973, UL 1998, and UL 9540 certification., * Derive small-signal plant models for buck, boost, and four-switch buck-boost topologies, and design discrete-time compensators (PID, type II/III, 2p2z/3p3z) to meet bandwidth, phase margin, and gain margin targets. * Implement control loops in C to fixed cycle budgets using fixed-point or single-precision arithmetic as appropriate, with explicit saturation, anti-windup, and bumpless mode transfer. * Architect and maintain the control ISR and scheduler - fast control task and slower supervisory task - with deterministic timing, measured jitter, and documented worst-case execution time. * Configure and validate the PWM, ADC, comparator, and DAC trigger architecture, including sampling instant placement relative to switching noise, trigger-to-response latency, dead-time, and hardware-independent cycle-by-cycle protection paths. * Implement operating mode arbitration: constant current, constant voltage, constant power, current limit, soft-start, buck-to-boost transition, phase shedding, and charge/discharge direction reversal. * Bring up new converter hardware in the lab, from first switching event through full envelope characterization, including gate-drive debug, dead-time optimization, and shoot-through avoidance. * Measure and correlate loop gain by network analyzer injection, step-load transient response, ripple, efficiency, and thermal derating behavior. * Build and maintain simulation and hardware-in-the-loop infrastructure sufficient to catch control regressions before hardware. * Author and maintain specifications, requirements, and verification evidence to a standard that withstands certification-body review. * Review control and embedded code written by others, and contribute to hardware design reviews covering the sense chain, ADC architecture, and protection paths.