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# Senior Systems Design Engineer - Qualcomm - Sophia or Guyancourt - France

- **Company:** Qualcomm
- **Location:** Guyancourt, France
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** C (Programming Language), C++ (Programming Language), Software Debugging, Linux, Microprocessors, Emulators, Field-Programmable Gate Array (FPGA), Python (Programming Language), SystemVerilog, Verilog, Application Specific Integrated Circuits, ModelSim
- **Published:** October 13, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=ffbf7eb2559c0943

## About the Role

Good RTL development skills: SystemVerilog/Verilog integration and design. RTL Simulation. Debugging

Systems understanding: Bus Protocols, DDR, SOC.

Emulation methodologies knowledge

Additional Skills:

Python, C, C++

Strong motivation and team spirit

Working environment: Linux, ModelSim

Educational Requirements:

Micro-electronics or similar Engineer Diploma

Minimum 5-10 years experience

Technical Experience:

Essential: Verilog/SystemVerilog, Verification Methodology

Desired: Python, Emulation

Language requirements: French and English, * Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience., Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.

 * References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

## Description

The engineer will be in charge of building and maintaining system level platforms for RTL simulation and FPGA Emulation. It includes the integration in systemVerilog of CPUs and/or NSP and infrastructure IPs such as interconnects or memory controllers. He will be responsible for designing RTL modules for the testbench such as traffic generators or DDR memory models coding in systemVerilog or C language (DPI-C). He will have to provide functional platforms by running and debugging integration and system level testcases. The engineer will also participate in mapping the full platform on various Emulators.