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# ASIC / VLSI Engineers

- **Company:** HI Etech Inc
- **Location:** Milpitas, CA, United States
- **Experience:** Expert
- **Salary:** $225,000.0
- **Contract:** Permanent contract
- **Skills:** Very-Large-Scale Integration, Boolean Algebra, Perl (Programming Language), Ethernet, Firmware, Python (Programming Language), Routing, Static Timing Analysis, SystemVerilog, Tcl (Programming Language), Scripting, Application Specific Integrated Circuits, Physical Design, Cts+
- **Published:** October 16, 2026
- **Apply:** https://www.thejobnetwork.com/job/f2eae947-4bce-4dd6-9127-fb21b0ad02ca/asic-vlsi-engineers

## About the Role

* 8+ years of pre-silicon ASIC / VLSI experience
 * Strong background in RTL-based design environments
 * Experience at the SoC / full-chip level (not IP-only)
 * Solid understanding of ASIC lifecycle (design * tapeout)
 * Scripting experience (Python, Tcl, Perl, etc.)
 * Strong digital logic fundamentals

Must have:

 * Pre-silicon experience only (no post-silicon / firmware-only backgrounds), * RTL design + microarchitecture
 * Ethernet (802.3), MAC / PCS / SerDes / PHY
 * High-speed designs (100G+ preferred)
 * Tapeout + productization experience

STA Engineer

 * SoC-level timing analysis & closure
 * PrimeTime, Tempus, or similar

Physical Design Engineer

 * Floorplanning, CTS, routing, signoff
 * Timing, congestion, power optimization

Design Verification Engineer

 * SoC-level verification (required)
 * SystemVerilog / UVM
 * Full verification lifecycle

What Sets You Apart

 * Experience with complex SoC / full-chip tapeouts
 * Ability to work cross-functionally (RTL, DV, PD)
 * Background in advanced nodes (28nm and below preferred)