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# SoC Top RTL Integration Engineer

- **Company:** Semidynamics
- **Location:** Barcelona, Spain (Remote available)
- **Contract:** Permanent contract
- **Skills:** Apple IOS, Computer Engineering, Software Debugging, Python (Programming Language), System on a Chip, SystemVerilog, Systems Integration, Verilog, Peripherals, Physical Design
- **Published:** October 27, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=71881b5ffb356cb4

## About the Role

* Degree in Electrical Engineering, Electronic Engineering, Computer Engineering or a related field.
 * 8+ years of experience in digital/SoC design.
 * Strong hands-on RTL design experience (SystemVerilog/Verilog).
 * Proven experience integrating multiple subsystems on large SoCs.
 * Experience connecting subsystems through interconnects and/or NoCs, with solid knowledge of AXI and APB.
 * Proven track record on one or more tape-outs.
 * Hands-on experience with lint, CDC and RDC checks.
 * Experience writing and managing SDC constraints and integrating chip IOs.
 * Working knowledge of Python and C for scripting and automation (user level).
 * Fluent English, written and spoken.

Nice to have

 * Knowledge of clock, reset and power architectures.
 * Experience with the CHI coherent interconnect protocol.
 * Experience with UPF-based low-power design flows and pad ring integration.

## Description

* Integrate multiple subsystems (CPU clusters, memory, accelerators, peripherals and third-party IP) into the SoC top-level RTL.
 * Connect subsystems through interconnects and NoCs using protocols such as AXI, APB and CHI.
 * Define and integrate the chip's IOs, including connections to pads.
 * Write and maintain SDC timing constraints for the integrated design, working with physical design teams.
 * Run, debug and close lint, CDC and RDC checks at SoC top level.
 * Integrate the top-level clock, reset and power infrastructure, and contribute to UPF power intent.
 * Develop Python and C scripts and tests to automate integration flows and support bring-up.
 * Work closely with architecture, verification, DFT and physical design teams to drive the SoC through to tape-out.