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# Integration Engineer

- **Company:** Business Integra
- **Location:** United States (Remote available)
- **Experience:** Experienced
- **Salary:** $156,000.0
- **Contract:** Permanent contract
- **Skills:** Adobe InDesign, Software Debugging, Perl (Programming Language), Python (Programming Language), Subsystems, SystemVerilog, Tcl (Programming Language), Verilog, Scripting, Data Server Interface, Application Specific Integrated Circuits, Physical Design
- **Published:** October 21, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=cb30bf7832fe5e6c

## About the Role

* Strong experience in ASIC/SoC RTL design and subsystem integration.
 * Hands-on expertise in Verilog and SystemVerilog.
 * Proven experience integrating multiple IPs and subsystems into complex SoC designs.
 * Strong understanding of connectivity, clock/reset architecture, CDC, and RDC.
 * Experience with RTL linting, structural checks, and RTL quality/signoff methodologies.
 * Good understanding of RTL hierarchy and design partitioning.
 * Experience collaborating with Physical Design teams and addressing PD-driven integration requirements.
 * Strong debugging, analytical, and problem-solving skills.
 * Ability to collaborate effectively across RTL, DV, DFT, and PD teams.

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Preferred Skills

 * Experience with Magillem or similar subsystem integration tools.
 * Experience with Network-on-Chip (NoC) IP.
 * Exposure to large-scale, multi-clock and multi-reset SoC designs.
 * Familiarity with synthesis, timing, low-power design/UPF, DFT, and implementation flows.
 * Scripting experience with Tcl, Python, Perl, or Shell.
 * Experience taking a subsystem from RTL integration through quality checks, signoff, and Physical Design handoff., * RTL linting, structural checks, and RTL quality/signoff : 2 years (Required)
 * integrating multiple IPs and subsystems into SoC designs: 2 years (Required)
 * Verilog and SystemVerilog: 2 years (Required)
 * ASIC/SoC RTL design and subsystem integration.: 2 years (Required)

## Description

We are seeking an experienced RTL Integration Engineer to support complex ASIC/SoC subsystem integration. The ideal candidate will have strong expertise in RTL/IP integration, subsystem connectivity, CDC/RDC closure, RTL quality checks, and collaboration with Physical Design and Verification teams., * Own subsystem-level RTL integration, including the integration of multiple IPs and functional blocks.

 * Implement and validate IP-to-IP and subsystem connectivity across clock, reset, control, and data interfaces.
 * Work with Magillem or similar tools for subsystem integration and connectivity management.
 * Drive closure of Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), RTL lint, structural checks, and connectivity validation.
 * Debug and resolve integration issues across multiple IP blocks.
 * Define and maintain clean RTL hierarchy and subsystem partitioning.
 * Collaborate with Physical Design (PD) teams on hierarchy, partitioning, implementation constraints, and integration requirements.
 * Work closely with RTL Design, Design Verification (DV), Design for Test (DFT), Architecture, and PD teams throughout integration and signoff.
 * Participate in design reviews, track integration issues, and ensure RTL readiness for downstream implementation.