> Markdown version of [/jobs/ext/4156180-senior-staff-digital-design-engineer-iv](https://www.wearedevelopers.com/jobs/ext/4156180-senior-staff-digital-design-engineer-iv). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

---

# Senior Staff Digital Design Engineer iv)

- **Company:** Infineon Technologies AG
- **Location:** Bristol, United Kingdom
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Logic Synthesis of Circuits, Hardware Description Language, SystemVerilog, Information Technology, Front End Software Development
- **Published:** October 28, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=f6bc02ec94327502

## About the Role

* A degree in Electronics/Electrical engineering, Computer Science, Physics or a similar field of studies
 * At least 5+ years of relevant design experience with a natural understanding in the field of complex digital IP design
 * Ability to develop RTL code targeting high speed and/or low area and understanding of how RTL will map to gate-level structures
 * Familiarity with the frontend design flow
 * Experience with hardware description languages - SystemVerilog would be desirable
 * Fluency in English (mandatory)

Please send us your CV in English.

## Description

As a Senior Staff Digital Design Engineer in our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life., As a Senior Staff Digital Design Engineer, you will develop and enhance digital products and modules including concept and circuit design as well as physical implementation and functional validation., * Generate complex Digital IP designs as well design related documentation, working alone or as part of a larger design team

 * Work with architects, verification and implementation engineers to fine-tune the design and lead to efficient verification and implementation cycles
 * Perform linting, RTL synthesis, and DFT insertion to prove the implementability of the design