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# Digital ASIC Architect

- **Company:** Apple Inc.
- **Location:** United States
- **Experience:** Expert
- **Salary:** $175,000.0 - $308,500.0
- **Contract:** Permanent contract
- **Skills:** C++ (Programming Language), Microarchitecture, Software Debugging, Digital Architecture, Digital Technology, Embedded Software, Firmware, Python (Programming Language), MATLAB, Micro Electro-Mechanical Systems (MEMS), Signal Processing, Subsystems, Systems Architecture, SystemC, Application Specific Integrated Circuits, Modeling and Simulation
- **Published:** October 10, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=5dc5430ca1e3044f

## About the Role

Deep expertise in digital ASIC architecture for sensor or mixed-signal systems, including processor and DSP sub-system definition, memory and bus architecture, and custom control engine micro-architecture

Proven track record of defining and taping out high-volume, complex digital and mixed-signal ICs from architecture through production

Strong foundation in system-level design, requirements development, and hardware/firmware partitioning for sensing or low-power embedded applications

Experience developing sensing algorithms and signal processing pipelines, with the modeling skills to evaluate them before silicon

Experience with IC bring-up, silicon characterization, and system-level debug

Proficiency in MATLAB, Python, C/C++, or SystemC for high-level modeling and simulation, BS in Electrical Engineering or related field with a minimum of 10 years of relevant industry experience

Excellent written and verbal communication skills

## Description

As a Digital ASIC Architect on the Motion Sensing Hardware team, you will own the digital architecture of motion sensing ASICs from concept through silicon, with the goal of delivering best-in-class sensing experiences across Apple's product line. You will analyze the application, then define cost and power optimized digital systems built around one or more processors, DSP cores, and custom control engines. You will translate high-level user and product requirements into a realizable system, build the high-level models that prove out the architecture, and author the detailed specifications that drive the rest of the IC development. This is a highly cross-functional role. You will work with circuit design, firmware, algorithms, software, and product teams to identify the critical interactions between the ASIC and the broader product, and you will produce the architectures and specifications that become the silicon Apple ships and the features customers feel.","responsibilities":"Define
the digital architecture needed to achieve the module ERS, including evaluation and down-selection of processor, DSP, memory, and interface IP and topologies against performance/power/area/risk

Perform trade-off analysis and interface with the Analog ASIC Architect, MEMS Architect, Firmware Lead, and SoC team for system-level architectural decision making

Define hardware/firmware partitioning, memory hierarchy, bus topology, clock and power domain structure, and peripheral integration

Lead digital architecture reviews with vendor and internal stakeholders

Develop sensing algorithms and signal processing pipelines, and build high-level models in MATLAB, Python, or SystemC to predict performance before RTL exists

Co-simulate digital with a behavioral analog front-end and MEMS model to validate full system interaction, then correlate models against first silicon to close the loop for the next iteration

Author IP-level and IC-level specifications that anchor design, verification, and characterization, including:

Processor, DSP, memory, bus, and custom control-engine requirements

Clocking, reset, power management, and I/O / peripheral specs

Host SoC and sensor AFE interface definitions

Drive defect root cause analysis and resolution from bring-up through mass production

Document architectural assumptions, open items, known risks, and waiver justifications for tape-out readiness sign-off

Communicate program status, technical issues, risks, and mitigation plans clearly and concisely

Minimal business travel as needed to support product development