> Markdown version of [/jobs/ext/4175387-asic-soc-dft-engineer-silicon-engineering](https://www.wearedevelopers.com/jobs/ext/4175387-asic-soc-dft-engineer-silicon-engineering). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

---

# ASIC/SOC DFT Engineer (Silicon Engineering)

- **Company:** Space Exploration Technologies Corp.
- **Location:** Palo Alto, CA, United States
- **Salary:** $135,000.0
- **Contract:** Permanent contract
- **Skills:** Bash Shell, Computer Engineering, Software Debugging, Perl (Programming Language), Firmware, Formal Verification, Python (Programming Language), Subsystems, SystemVerilog, Verilog, Scripting, Application Specific Integrated Circuits, Information Technology, Physical Design
- **Published:** October 1, 2026
- **Apply:** https://www.careerbuilder.com/job-details/asic-soc-dft-engineer-silicon-engineering-palo-alto-ca--7f2dc2d2-a401-400f-884f-b128f556bbb3

## About the Role

* Bachelor's degree in electrical engineering, computer engineering or computer science
 * 1+ years of professional experience working with ASICs
 * Experience in scan insertion or DFT setup

PREFERRED SKILLS AND EXPERIENCE:

 * Understanding of ASIC design flow, methodologies, physical design, and verification
 * Experience with high reliability design and implementations
 * Good scripting skills (csh/bash, Perl, Python etc.)
 * Familiar with implementation or integration of design blocks using Verilog/SystemVerilog
 * Familiar with UPF (unified power format), formal verification, and DRC rule checking experience
 * Ability to work in a dynamic environment with changing needs and requirements
 * Team-player, can-do attitude, and ability to work well in a group environment while still contributing on an individual basis
 * Enjoys being challenged and learning new skills, * To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

## Description

* Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
 * Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
 * Running and evaluating scan insertion through synthesis tools and refining scan insertion recipe for maximum coverage
 * Run ATPG(Automatic Test Pattern Generation) analysis to ensure quality scan chain construction and meeting basic coverage goals
 * Run and debug non-timing and SDF annotated gate level simulations
 * Creating ATPG content for use in post-silicon testing and validating that content through gate level simulation
 * Collaborate with circuit physical design team, ATPG team and manufacturing team to facilitate high quality scan coverage in silicon