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# Sr. Designer Engineer (ASIC/FPGA)

- **Company:** VARSTAFF LLC
- **Location:** El Segundo, CA, United States
- **Experience:** Expert
- **Contract:** Temporary contract
- **Skills:** Computer Engineering, Electronic Design Automation, Perl (Programming Language), Firmware, Field-Programmable Gate Array (FPGA), Hardware Description Language, Python (Programming Language), Object-Oriented Software Development, Static Timing Analysis, SystemVerilog, Tcl (Programming Language), Verilog, VHSIC Hardware Description Language (VHDL), Scripting, Application Specific Integrated Circuits, Linux Development, Physical Design, Software Defined Radio
- **Published:** October 7, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=b7f3e75dbae9b9f5

## About the Role

* 7+ years of ASIC design and implementation experience.
 * Bachelor's degree in Electrical Engineering, Computer Engineering or a related technical discipline.
 * FPGA and ASIC design experience.
 * Proficiency in HDL (VHDL, Verilog and/or SystemVerilog).
 * Linux development environment experience.
 * Design verification and test bench development experience., * MS or PhD in Electrical Engineering, Computer Engineering or a related field.
 * Full ASIC/FPGA lifecycle experience (architecture, design, simulation, verification, validation, integration and test).
 * Software-defined radio architectures, ADC/DAC and/or DSPs.
 * DSP and communications systems knowledge: spread spectrum, forward error correction, modulation types (QPSK, QAM, PCM/FM, PAM).
 * Strong object-oriented programming and scripting (Python, TCL, Perl).
 * Physical design flows and industry-standard EDA tools; RTL-to-GDSII physical design and signoff.
 * Deep sub-micron FinFET and CMOS technologies.
 * DFT/Scan/MBIST/LBIST methodologies.
 * Mentoring junior engineers.

## Description

* Design and develop digital ASICs and FPGAs and/or mixed-signal ASICs.
 * Implement designs in HDL (VHDL, Verilog and/or SystemVerilog).
 * Develop verification methodologies and test benches for block- and system-level verification.
 * Create and execute test plans, develop test harnesses and implement coverage models.
 * Conduct timing analysis, noise analysis and other signoff checks.
 * Collaborate with systems, firmware, architecture and product engineering teams.
 * Support lab integration and troubleshooting.
 * Resolve timing, congestion and other implementation issues.