> Markdown version of [/jobs/ext/4216248-staff-logic-design-engineer](https://www.wearedevelopers.com/jobs/ext/4216248-staff-logic-design-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

---

# Staff Logic Design engineer

- **Company:** Teledyne Technologies Inc
- **Location:** Milpitas, CA, United States
- **Experience:** Expert
- **Salary:** $141,900.0 - $189,200.0
- **Contract:** Permanent contract
- **Skills:** Adobe InDesign, Boolean Algebra, Code Review, Computer Engineering, Microarchitecture, Software Debugging, Logic Synthesis of Circuits, Ethernet, Serial ATA, Firmware, Field-Programmable Gate Array (FPGA), Python (Programming Language), Packet Analyzer, PCI Express, SAS (Software), SystemVerilog, Systems Integration, Tcl (Programming Language), USB, Verilog, Vivado, Scripting, Application Specific Integrated Circuits, Fpga Hardware, ModelSim, Decoding, Nvme
- **Published:** October 11, 2026
- **Apply:** https://www.juju.com/job/1_teledyne6-REQ31773

## About the Role

You'll work on FPGA-based systems that decode and analyze High speed protocols (PCIe, USB, Ethernet etc.) in real time, collaborating with cross-functional teams to deliver industry-leading solutions. **Key Responsibilities** + **RTL Design & Microarchitecture** + Develop synthesizable RTL (Verilog/SystemVerilog) for high-speed protocol, packet parsing, timestamping, and buffer management. + Design high-throughput data paths and control logic optimized for latency, bandwidth, and resource efficiency. + **FPGA Development** + Target high-end FPGAs (Xilinx Versal, Intel Agilex); perform synthesis, P&R, timing closure, and resource optimization. + Integrate PCIe IP cores, DMA engines, and custom protocol decoders. + **Verification & Debug** + Build SystemVerilog/UVM testbenches for block and system-level verification. + Conduct simulation, waveform analysis, and functional coverage to ensure robust design. + **System Integration** + Collaborate with hardware, firmware, and
software teams to bring up and validate protocol analyzer platforms. + Support lab debug using logic analyzers, oscilloscopes, and in-system FPGA tools (ILA/SignalTap). + **Documentation & Process** + Create design specifications, interface documents, and verification plans. + Participate in design/code reviews and contribute to continuous improvement of design practices. **Required Qualifications** + BS in EE, CS or Computer Engineering required + MS in EE is a plus + **7+ years** of experience in digital logic design for FPGA or ASIC. + Strong proficiency in **Verilog/SystemVerilog RTL design** . + Experience with one or more of the following protocols: **PCIe, CXL, NVMe, USB, SAS, SATA ** + Experience with Monitoring and/or Test & Measurement tools + Experience with **PCIe protocol** (Gen4/Gen5/Gen6) and familiarity with TLP/DLLP/PHY layer concepts. + Hands-on with **FPGA toolchains** (Vivado, Quartus, etc.) and timing closure. + Knowledge of **UVM** ,
assertions, and simulation/debug tools (e.g., ModelSim, Vivado Simulator). + Solid understanding of **CDC** , clock domain design, and reset strategies. **Preferred Qualifications** + Experience with **protocol analyzers** , packet capture, and timestamping logic. + Familiarity with **AXI interconnects** , memory controllers, and high-speed buffering. + Exposure to **SERDES** , PCIe IP integration, and link training/debug. + Scripting experience (Python, Tcl) for automation and test infrastructure. + Experience with **hardware/software co-design** , register maps, and embedded firmware interaction. + Prior work in **test & measurement** or **semiconductor validation** environments. **Work Environment** + **Location:** Milpitas, CA + **Travel:** Minimal (10%) for lab collaboration or customer support + **Team Culture:** Collaborative, fast-paced, and innovation-driven **Salary Range:** $141,900.00-$189,200.000 **Pay Transparency** The anticipated salary