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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # TPU RTL Design Engineer, Google Cloud - **Company:** Google LLC - **Location:** Sunnyvale, CA, United States - **Experience:** Experienced - **Salary:** $138,000.0 - $197,000.0 - **Contract:** Permanent contract - **Skills:** Data Analysis, Bioinformatics, Computer Engineering, Microarchitecture, Software Debugging, Electronic Design Automation, Perl (Programming Language), Python (Programming Language), CPU Design, SystemVerilog, Tcl (Programming Language), Google Cloud, Application Specific Integrated Circuits, Information Technology, Power Analysis (Cryptography), Physical Design - **Published:** October 3, 2026 - **Apply:** https://www.techcareers.com/job.asp?id=3417355841&tx=FP8178FFQ&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54 ## About the Role Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area., * Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 2 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development. * Experience in SystemVerilog for creating microarchitecture specifications and synthesizable RTL. * Experience using Python, Tcl, or Perl for automating design tasks and data analysis. * Experience with industry-standard EDA tools for simulation, synthesis, and power analysis., * Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. * 5 years of experience with high-performance ASIC design in Phase-Locked Loop, Frequency-Locked Loop, and Delay-Locked Loop integration. * Experience implementing clock skipping, Dynamic Voltage and Frequency Scaling (DVFS), and fine-grained clock gating for low-power SoC optimization. * Knowledge of processor design or accelerators and of high-performance and low power design techniques. * Understanding of clock distribution challenges, including jitter, skew management, and duty-cycle distortion. * Proficiency in Python or Perl for automating design scripts and analyzing complex clock-tree data. ## Description * Work independently to create and review clock control subsystem's design micro-architecture specifications. * Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines. * Work with architecture and power teams to evaluate features and their impact. * Work with Design Validation (DV) teams to create test plans to verify and debug design RTL. * Work with physical design teams to ensure design meets physical requirements and timing closure. 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