> Markdown version of [/jobs/ext/4221465-eng-sr-prin-ii-elec](https://www.wearedevelopers.com/jobs/ext/4221465-eng-sr-prin-ii-elec). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Eng Sr Prin II - Elec - **Company:** BAE Systems - **Location:** Manchester, NH, United States - **Experience:** Expert - **Contract:** Temporary contract - **Skills:** C++ (Programming Language), IBM Rational ClearCase, Computer Engineering, Microarchitecture, Software Debugging, Perl (Programming Language), Field-Programmable Gate Array (FPGA), Python (Programming Language), Unix Shell, MATLAB, PCI Express, Subversion, SystemVerilog, Tcl (Programming Language), Verilog, VHSIC Hardware Description Language (VHDL), Vivado, Application Specific Integrated Circuits, Fpga Hardware, ModelSim, Git, SC Clearance, Software Version Control - **Published:** October 7, 2026 - **Apply:** https://www.careerjet.com/job/us8369d0c57c918055bc1c4bf014ff16f7/eaa ## About the Role Typically a Bachelor's Degree and 10 years work experience or equivalent experience, * 10+ years of relevant experience with bachelor's degree (less with an advanced degree) * Current Security Clearance (Secret), or eligible to obtain one * Ability to distill higher level requirements into micro-architecture * Extensive experience in FPGA (preferred) or ASIC Design / Development * Experience leading/managing a design team * Experience with DSP fundamentals * Working understanding of Radar systems and/or EW systems * Proficient in VHDL (preferred) or Verilog HDL coding * Familiarity with Xilinx Vivado/ISE or Altera Quartus * Digital simulation using Modelsim/Questa * Strong understanding of timing driven design including clock domain crossing circuitry * Strong lab debug and problem solving skills * Strong written and oral communication skills * Ability to mentor and willingness to be mentored * Experience with high-speed interfaces like PCIe, SerDes, ADC/DAC, DDR3/4 * Familiarity with revision control (GIT, CVS, Clearcase, Subversion, etc.) * Proficient in Tcl/Tk and UNIX/Linux shell programming Preferred Skills and Education * Experience with FPGA implementation * Experience with Matlab/Simulink * Experience creating unique designs and supporting legacy designs * Experience with UVM/System Verilog * Some experience with managing schedule and cost is beneficial * Experience with C/C++, Perl and Python ## Description Electronic Combat Solutions Hardware Engineering Group is seeking a Senior Principal II FPGA Design Engineer to lead and develop a team of FPGA designer engineers through all phases of development. The ideal candidate is expected to perform activities including requirements generation and design architecture; technical oversight and mentoring of team members; as well as ownership of RTL coding, synthesis, basic test bench development, lab testing, and product support. BAE offers competitive pay, benefits and important work-life balance initiatives including every other Friday off and flex time. BAE also believes in a culture of recognition for extraordinary contributions or our skilled employees. Because of the need for consistent, in-person collaboration and the requirement to perform all work onsite due to the nature of this particular role, it will be performed full-time on site. **Please not that pursuant to a government contract, along with the ability to obtain a minimum of Secret Clearance** Postal Code 03064-2813 Job Family Electrical Eng Travel Percentage Clearance Level - Must be able to obtain for position Secret Shift 1st Shift Regular or Temporary Regular Typical Education and Experience