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# Senior Technical Architect

- **Company:** HCL America, Inc.
- **Location:** United States
- **Experience:** Expert
- **Salary:** $95,000.0 - $192,000.0
- **Contract:** Permanent contract
- **Skills:** Software Debugging, Perl (Programming Language), Static Timing Analysis, Tcl (Programming Language), Linux Virtual Server, Scripting, Physical Design, Cts+
- **Published:** October 15, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=9c44d2322f2f1f08

## About the Role

* Strong expertise in Synopsys ICC2/Fusion Compiler or Cadence Innovus
 * Advanced floorplanning and partitioning knowledge
 * Timing closure expertise
 * Full-chip integration and hierarchical design methodologies
 * TCL, Perl, Python scripting
 * Excellent debugging and stakeholder management skills
 * Experience with advanced process nodes (16nm and below preferred)

Must Have Skill

Physical Design,Static Timing Analysis (STA)

## Description

Leads block-level and top-level physical implementation, driving design closure from netlist to GDS while coordinating cross-functional teams. Also owns full-chip integration activities., * Manage floorplanning, placement, CTS, routing, and signoff closure

 * Drive PPA (Power, Performance, Area) optimization
 * Full-chip assembly and hierarchical integration
 * Resolve timing, congestion, IR, EM, DRC/LVS issues
 * Coordinate with RTL, STA, DFT, Package, and Verification teams
 * Tape-out planning and execution
 * Mentor physical design engineers