> Markdown version of [/jobs/ext/4231948-sr-pd-methodology-engineer-annapurna-labs-cloud-scale-machine-learning](https://www.wearedevelopers.com/jobs/ext/4231948-sr-pd-methodology-engineer-annapurna-labs-cloud-scale-machine-learning). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

---

# Sr. PD Methodology Engineer, Annapurna Labs - Cloud Scale Machine Learning

- **Company:** Annapurna Labs
- **Location:** Cupertino, CA, United States
- **Experience:** Expert
- **Salary:** $185,200 - $287,500
- **Contract:** Permanent contract
- **Skills:** Computer-Aided Design, Amazon Web Services, Cloud Computing, Continuous Integration, Data Centers, Software Debugging, Formal Verification, Python (Programming Language), Machine Learning, Performance Tuning, System on a Chip, Tcl (Programming Language), Scripting, Application Specific Integrated Circuits, AWS Trainium, Physical Design, Software Version Control
- **Published:** October 19, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=3303eb34ab09804a

## About the Role

* 7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience
 * Bachelor's degree in Electrical Engineering or a related field
 * Knowledge of implementing chips with multiple power islands and power gating
 * Experience leading or solely developing methodology and scripts for physical synthesis
 * Experience low power design techniques
 * Experience leading technical initiatives and key deliverables
 * Experience with version control systems and CI/CD pipeline implementation

PREFERRED QUALIFICATIONS

 * Master's degree or Ph.D. degree in Electrical Engineering or related field
 * Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs

## Description

Custom SoCs (System on Chip) live at the heart of Amazon Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, Trainium Systems (our custom designed machine learning inference and training datacenter servers). Our success depends on our world-class server infrastructure; we're handling massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs., Define, develop and deploy innovative physical design and verification methodologies (RTL2GDS) for ML Accelerator chips in advanced nodes

Drive Optimizations in CAD flows/methodologies for PPA and TAT improvements

Work with EDA tool vendors to evaluate new methods, resolve bugs, improve usability.

Fine tune cloud infrastructure to improve compute and storage utilization for physical design work.

Interface directly with RTL, Physical Design, Package Design, DFT teams to improve methodologies and efficiencies.

Be able to independently troubleshoot digital tool flow usage and deploy solutions;

Fluent in scripting languages such as TCL, Python, etc. and able to build scalable and efficient flows to support parallel design developments

Create Dashboard and Central reports for project tracking and visualizing QoR/stats