> Markdown version of [/jobs/ext/4247576-performance-modeling-engineer](https://www.wearedevelopers.com/jobs/ext/4247576-performance-modeling-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

---

# Performance Modeling Engineer

- **Company:** Etched, LLC
- **Location:** San Jose, CA, United States
- **Salary:** $175,000.0
- **Contract:** Permanent contract
- **Skills:** Audit Trail, Profiling, Nvidia CUDA, Computer Programming, Microarchitecture, Field-Programmable Gate Array (FPGA), High-Level Architecture, Graphics Processing Unit (GPU), Application Specific Integrated Circuits, Deep Learning, Hardware Acceleration, Machine Learning Operations
- **Published:** October 22, 2026
- **Apply:** https://www.thejobnetwork.com/job/cdb42541-cc3a-4cd9-afe2-e0e5874aaf47/performance-modeling-engineer

## About the Role

* Strong performance modeling and analysis skills with experience building analytical-based or simulation-based performance models
 * Solid understanding of computer architecture and micro-architecture, particularly for accelerators
 * Experience profiling and analyzing deep learning workloads on hardware accelerators (GPUs, TPUs, ASICs, FPGAs, or others)
 * Solid software engineering fundamentals with an eye toward auditability and maintainability

Strong candidates may also have

 * Deep knowledge of GPU architectures and/or programming models like CUDA
 * Experience mapping models to multi-chip inference systems
 * Familiarity with transformer model architectures and inference serving optimizations
 * Experience with architecture simulators and performance modeling tools (gem5, trace-driven simulators, custom models)
 * Exposure to ASIC, FPGA, or CGRA-based accelerator development and hardware/software co-design principles
 * Published research in computer architecture, ML systems, or hardware acceleration

## Description

* Develop comprehensive performance models and projections for our architecture across varying workloads and configurations
 * Profile and analyze deep learning workloads on our hardware to identify micro-architectural bottlenecks and influence optimization opportunities
 * Drive hardware/software co-optimization by identifying where architectural features can unlock performance improvements
 * Run regressions and validate performance models against real systems and silicon
 * Inform next-generation architectural decisions by pathfinding across system and silicon options during design, proof-of-concept, and architecting phases