> Markdown version of [/jobs/ext/4255394-asic-architect](https://www.wearedevelopers.com/jobs/ext/4255394-asic-architect). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # ASIC Architect - **Company:** Etched, LLC - **Location:** San Jose, CA, United States - **Experience:** Expert - **Salary:** $200,000.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, C++ (Programming Language), Computer Engineering, Data Flow Control, Python (Programming Language), SystemC, SystemVerilog, Verilog, Application Specific Integrated Circuits, Information Technology, Low Latency, Machine Learning Operations, Physical Design - **Published:** October 21, 2026 - **Apply:** https://www.thejobnetwork.com/job/8d019545-f978-404c-9326-bf4f89eb7b50/asic-architect ## About the Role * PhD in Computer Science, Electrical Engineering, Computer Engineering, or related field * 5+ years of experience in computer architecture, ASIC design, or related fields * Strong understanding of computer architecture fundamentals including pipelines, memory hierarchies, and interconnects * Experience with performance modeling and architectural simulation tools * Hands-on experience designing and optimizing floating-point datapaths or arithmetic-intensive circuits and working with advanced process nodes. * Proficiency in Rust, C/C++, or Python for modeling and analysis * Knowledge of modern processor microarchitecture and design tradeoffs * Strong analytical and problem-solving skills with attention to detail * Excellent communication skills and ability to work in cross-functional teams Strong candidates may also have experience with * AI/ML accelerator architectures and dataflow optimization * RTL design and verification (Verilog/SystemVerilog) * Cycle-accurate simulation tools (gem5, SystemC, or custom simulators) * Power and performance analysis methodologies * ASIC design flow and physical design constraints * Publishing or presenting at architecture conferences (ISCA, MICRO, HPCA, etc.) * Hands-on experience with tapeout and silicon bring-up ## Description We are seeking a talented Computer Architect to join our architecture team and contribute to the design of next-generation AI accelerators. This role focuses on developing and optimizing compute architectures that deliver exceptional performance and efficiency for inference workloads. You will work on cutting-edge architectural problems and performance modeling with deep cross-functional collaboration to bring innovative chip designs from concept to silicon., * Design and analyze chip architectures optimized for AI/ML workloads, with focus on throughput, latency, and power efficiency * Contribute to power and area estimation methodologies for early-stage, next generation architectural exploration * Create architectural specifications and interface definitions for compute blocks and subsystems * Collaborate with RTL, verification, physical design, and software teams to ensure architectural feasibility and ultimate optimization * Conduct architectural experiments using cycle-accurate simulators and analytical models * Support integration efforts by providing architectural guidance and resolving design challenges