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# NAND Array Engineer

- **Company:** SK Hynix Nand Product Solutions Corp.
- **Location:** San Jose, CA, United States
- **Experience:** Experienced
- **Salary:** $139,520.0 - $255,000.0
- **Contract:** Permanent contract
- **Skills:** C (Programming Language), Data Analysis, Bit Error Rate, C++ (Programming Language), Computer Programming, Experimental Data, Python (Programming Language), Machine Learning, JMP (Statistical Software)
- **Published:** October 11, 2026
- **Apply:** https://www.juju.com/job/16_cc495f681

## About the Role

* Master's or PhD in Electrical Engineering, Microelectronics, or a closely related field.
 * 3+ years of industry experience in semiconductor memory technologies and products.
 * Deep understanding of NAND cell and array operations, including array reliability physical mechanisms and characterization techniques.
 * Strong foundation in semiconductor device physics and process flows.
 * Proficiency in statistical analysis methodologies and tools.
 * Hands-on programming experience in C, C++, Python, and/or JMP.
 * Proven ability to thrive in a fast-paced, cross-functional team environment.
 * Strong analytical and problem-solving skills with attention to detail.
 * Excellent communication and presentation skills, with the ability to convey complex technical concepts to diverse audiences., * Experience with 3D NAND architecture and advanced memory scaling challenges.
 * Familiarity with wafer fab processes and Sort/WLR test methodologies.
 * Track record of releasing trims or process improvements to high-volume manufacturing.
 * Experience with machine learning or advanced modeling techniques for semiconductor data.

## Description

Solidigm is looking for a highly motivated and technically skilled NAND Array Engineer to join our Performance and Reliability Team. In this role, you will play a critical part in shaping the future of 3D NAND technology by driving characterization of array erase, program, and read operations, and leading trim development for next-generation products. You will work at the intersection of device physics, data analysis, and cross-functional collaboration to deliver industry-leading NAND solutions., * Design, plan, and execute NAND memory cell and array characterization experiments to evaluate performance and reliability.

 * Develop and optimize trims to improve Read Window Budget (RWB) and Raw Bit Error Rate (RBER), directly impacting product quality.
 * Apply NAND device physics principles to explain and interpret relationships between experimental data and trim parameters.
 * Collaborate cross-functionally with Device, Design, Reliability, and Product/Test Engineering teams to design and execute bench experiments.
 * Interface with wafer fabrication teams to drive Sort and Wafer-Level Reliability (WLR) Design of Experiments (DOEs).
 * Conduct comprehensive data analysis to identify and communicate trade-offs across multiple parameters of interest.
 * Build predictive models for NAND behavior based on empirically observed data.
 * Develop and maintain scorecards to track NAND device degradation through various physical mechanisms over time.
 * Release optimized trims to the production flow on a regular cadence to ensure continuous product improvement.
 * Drive improvements in back-end test yields through trim optimization and advanced screening techniques.