> Markdown version of [/jobs/ext/4282347-hardware-security-engineer-hyperscaler-security-hybrid](https://www.wearedevelopers.com/jobs/ext/4282347-hardware-security-engineer-hyperscaler-security-hybrid). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

---

# Hardware Security Engineer - Hyperscaler Security Hybrid

- **Company:** Cisco Systems, Inc.
- **Location:** Durham, NC, United States
- **Salary:** $132,800.0 - $185,100.0
- **Contract:** Permanent contract
- **Skills:** BIOS, Computer Engineering, Software Debugging, Digital Signature, Firmware, Field-Programmable Gate Array (FPGA), Hardware Design, Hardware Security Module, Joint Test Action (IEEE Standards), Secure Coding, Cloud Platform System, Cyber Threat Analysis, Information Technology, U-Boot, Cisco
- **Published:** October 22, 2026
- **Apply:** https://www.techcareers.com/job.asp?id=3472086911&tx=FP1108FFK&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54

## About the Role

* Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field with 7+ years of relevant experience (or Master's degree with 4+ years of experience, or PhD with 1+ year of relevant experience).
 * Prior background in hardware development (e.g. reading and interpreting system-level schematics, block diagrams, component datasheets, PCB design or review, or register-level hardware documentation).
 * Prior background in hardware security fundamentals, such as Hardware Root of Trust (RoT), Secure Boot, hardware and firmware resiliency, cryptographic primitives (symmetric/asymmetric encryption, hashing, digital signatures), or secure key storage., * Experience with crafting, implementing, or evaluating hardware-rooted attestation architectures and device identity mechanisms (e.g., SPDM, TCG DICE, etc.).
 * Experience with Hyperscaler and cloud platform architectures (e.g., OCP specifications, OpenBMC, Caliptra, OpenTitan, OpenPRoT, etc.).
 * Experience implementing industry standard security IP or developing novel HW security solutions (e.g. FPGA bitstream security, secure microcontroller architectures, HW RoT, bus encryption).
 * Experience with hardware threat modeling or hardware security analysis (e.g., fault injection, side-channel analysis, JTAG/debug security).
 * Background in hardware security frameworks and standards, such as NIST SP 800-193, NSA CNSA 2.0, TCG DICE / TPM, or global cybersecurity regulations (e.g., EU CRA).

## Description

You are a collaborative hardware engineer with a background in hardware design, low-level architecture, and security principles. You enjoy translating complex technical standards into practical engineering requirements and partnering across disciplinary boundaries to solve complicated hardware security problems. You communicate technical concepts clearly through engineering documentation and multi-functional collaboration, and you thrive when driving multiple parallel technical initiatives in a dynamic environment.

 * System-to-Silicon Security Analysis: Evaluate system-level hardware designs, schematics, board architectures, and component datasheets to identify threat vectors, vulnerabilities, and compliance gaps.
 * Standards & Regulatory Translation: Interpret, apply, and establish requirements aligned with emerging industry standards and compliance frameworks, including NIST SP 800-193 (Platform Firmware Resiliency), NSA CNSA 2.0 (Post-Quantum Cryptography / CNSA Suite), the EU Cyber Resilience Act (CRA), and internal Hardware Cisco Secure Development Lifecycle (HW-CSDL) mandates.
 * Technical Guidance & multi-functional Influence: Serve as a technical advisor, providing clear, actionable security requirements and architectural design guidance to product teams, hardware design engineers, firmware/BIOS teams, and third-party vendors.
 * Documentation & Technical Collateral: Author hardware security requirements, review checklists, threat models, compliance white papers, and engineering specifications for internal and external consumption.
 * Multi-Stream Project Engagement: Participate in and manage multiple concurrent security evaluations, design reviews, and compliance workstreams across diverse hardware programs.