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# Senior FPGA Engineer

- **Company:** Randstad
- **Location:** Cedar Rapids, IA, United States
- **Experience:** Expert
- **Salary:** $104,000.0 - $141,856.0
- **Contract:** Contract
- **Skills:** Agile Methodology, JIRA, Bioinformatics, Software Debugging, Digital Electronics, Field-Programmable Gate Array (FPGA), Subversion, Verilog, VHSIC Hardware Description Language (VHDL), Vivado, Application Specific Integrated Circuits, Fpga Hardware, Git, Software Version Control
- **Published:** October 22, 2026
- **Apply:** https://www.randstadusa.com/jobs/141/1365389/senior-fpga-engineer_cedar-rapids/

## About the Role

STEM degree with 5+ years of relevant experience (or Advanced Degree with 3+ years), including at least 3 years in FPGA development or ASIC front end. Proficient in VHDL/Verilog for digital circuit architecture, timing closure, resource tradeoffs, and FPGA toolchains such as Vivado, Quartus, or Libero. Strong system debugging skills alongside experience using revision control tools like Git or Subversion.

## Description

job summary:
Join Our Client as a Senior FPGA Engineer a leader in defense tech! We are seeking a STEM-degreed contractor with 5+ yrs experience and VHDL/Verilog skills in FPGA design, verification, and integration. Build cutting-edge solutions today!

location: Cedar Rapids, Iowa
job type: Contract
salary: $50.00 - 68.20 per hour
work hours: 8am to 5pm
education: Bachelors

responsibilities:

 * Design, verify, and integrate high-performance digital FPGA solutions onto target hardware units.
 * Participate in Agile team meetings, program planning activities, and development workflows.
 * Support peer reviews and certification analysis for FPGA development artifacts.
 * Manage change requests, task assignments, and workflow tracking through Jira.
 * Adhere to established engineering development procedures, quality processes, and guidelines.

qualifications:
STEM degree with 5+ years of relevant experience (or Advanced Degree with 3+ years), including at least 3 years in FPGA development or ASIC front end.

Proficient in VHDL/Verilog for digital circuit architecture, timing closure, resource tradeoffs, and FPGA toolchains such as Vivado, Quartus, or Libero.

Strong system debugging skills alongside experience using revision control tools like Git or Subversion.

Equal Opportunity Employer: Race, Color, Religion, Sex, Sexual Orientation, Gender Identity, National Origin, Age, Genetic Information, Disability, Protected Veteran Status, or any other legally protected group status.

At Randstad, we welcome people of all abilities and want to ensure that our hiring and interview process meets the needs of all applicants. If you require a reasonable accommodation to make your application or interview experience a great one, please contact HRsupport@randstadusa.com.

Pay offered to a successful candidate will be based on several factors including the candidate's education, work experience, work location, specific job duties, certifications, etc. In addition, Randstad offers a comprehensive benefits package, including: medical, prescription, dental, vision, AD&D, and life insurance offerings, short-term disability, and a 401K plan (all benefits are based on eligibility).

This posting is open for thirty (30) days.

,

 * Design, verify, and integrate high-performance digital FPGA solutions onto target hardware units.
 * Participate in Agile team meetings, program planning activities, and development workflows.
 * Support peer reviews and certification analysis for FPGA development artifacts.
 * Manage change requests, task assignments, and workflow tracking through Jira.
 * Adhere to established engineering development procedures, quality processes, and guidelines.