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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # ASIC Design Verification Engineer (Security Group) - Sr Staff - **Company:** Qualcomm - **Location:** Santa Clara, CA, United States (Remote available) - **Experience:** Expert - **Salary:** $190,200.0 - $285,400.0 - **Contract:** Permanent contract - **Skills:** Assembly Language, Microarchitecture, Software Debugging, Logic Synthesis of Circuits, Microprocessors, Perl (Programming Language), Fault Tolerance, Formal Verification, Field-Programmable Gate Array (FPGA), Make (Software), Python (Programming Language), Regression Analysis, Reduced Instruction Set Computing, Software Requirements Analysis, Specman, Subsystems, SystemVerilog, Unix Commands, Visual Systems, Scripting, Application Specific Integrated Circuits, Physical Design - **Published:** October 23, 2026 - **Apply:** https://www.indeed.com/viewjob?jk=33bc86232f4eae94 ## About the Role Minimum Experience Level should be 10+ years in SOC-level verification with good understanding of debugging either ARM-based or RISC-V based processors, good understanding of APB/AHB/AXI protocols. Must have solid understanding of SV/UVM concepts. Prior experience in any cryptographic algorithm is preferred. Must have basic understand on UNIX commands and Python/Perl scripting., * SystemVerilog * UVM * Synopsys VCS/Verdi * Makefile automation * Python scripting * Assertion-based verification * Functional coverage, * Deep knowledge of APB/AXI/SPI protocols, handshake mechanisms, cross-clock domains and clock gating. * Solid understand of memory organization, fault-tolerant design, parity schemes, error detection and error correction schemes. * Advance techniques such as: Formal, Assertions, and Silicon bring-up, is helpful. * In-depth knowledge of Micro-processor functions, Network-on-Chip Architectures, and Micro-architectures. * Experience in writing Test plans, portable Testbenches, Transactors, and Assembly code. * Experience with different Verification Methodologies and Tools such as Simulators, Coverage collection, Gate-level Simulation, Waveform viewers, and Mixed signal Verification. * Ability to develop and work independently on a Block/Unit of the design., * Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience., Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. ## Description As a leading technology innovator, Qualcomm pushes the boundaries to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements., As a Design Verification Engineer, you will work with Chip Architects to validate the concepts of core and sub-system level micro-architectures. You will work on a selected part of the subsystem Design Verification to ensure that it functions to the standards of being launch ready for the end Product. Role and Responsibilities * Work with subsystem and SOC Architects to understand the concepts and high-level system requirements. * Develop detailed Test and Coverage plans based on the Architecture and Micro-architecture. * Develop Verification Methodology, ensuring scalability and portability across environments. * Develop Verification environment, including all the respective components such as Stimulus, Checkers, Monitors Assertions, and Coverpoints. * Develop Verification Plans and Testbenches for your functional domain. * Execute Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions enabling all features under your care, and Debug of the test failures. * Track and report DV progress using a variety of metrics, including Bugs and Coverage., * Leverage advanced knowledge of computer architecture, micro-architecture, logic design, circuits, and/or physical design to develop and verify critical high performance and secure designs * Anticipate, identify, and solve highly-complex problems to ensure design completeness, functionality, power, and performance. * Collaborate with cross-functional teams to define requirements, specifications, and trade-offs (e.g., performance, power, cost, functionalities, etc.) in order to accomplish product goals. * Evaluates all aspects of the design process from conceptualization to productization (i.e., architecture definition, feasibility, pre-silicon design and verification, and post-silicon validation) that meet customer and industry standards. * Writes detailed technical documentation (e.g., feature descriptions, architectural descriptions, verification test plans, and implementation details, etc.) for highly complex secure subsystem designs; reviews documentation of junior engineers. * Propose meetings and technical discussions to review Test Plans, debug issues and incorporate feedback into existing documentation and Test Plans. * Run and Analyze Coverage reports, understand Coverage holes and re-spin Test Plans to achieve coverage metrics. Level of Responsibility: * Work independently with minimal supervision. * Provide supervision/guidance to other team members. * Decision-making is significant in nature and affects work beyond immediate work group. * Require verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. * Has a moderate amount of influence over key organizational decisions. * Tasks do not have pre-defined steps; planning, problem-solving, and prioritization must occur to complete the tasks effectively.