> Markdown version of [/jobs/ext/4315812-senior-engineer-digital-design-engineering](https://www.wearedevelopers.com/jobs/ext/4315812-senior-engineer-digital-design-engineering). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Senior Engineer, Digital Design Engineering - **Company:** Analog Devices - **Location:** United States - **Experience:** Expert - **Salary:** $116,960.0 - $160,820.0 - **Contract:** Permanent contract - **Skills:** Adobe InDesign, C Sharp (Programming Language), C++ (Programming Language), Computer Engineering, Software Debugging, Digital Arts, Digital Electronics, Digital Data, Logic Synthesis of Circuits, Field-Programmable Gate Array (FPGA), Design of User Interfaces, Python (Programming Language), Radio-Frequency Identification, PCI Express, Schematic Capture, Signal Integrity, Subsystems, Tcl (Programming Language), Technical Data Management Systems, Verilog, VHSIC Hardware Description Language (VHDL), Application Specific Integrated Circuits, SC Clearance, Pcb Layout - **Published:** October 22, 2026 - **Apply:** https://www.oriontalent.com/search-jobs/career/11686715/senior-engineer-digital-design-engineering-massachusetts-ma-elizabeth ## About the Role This position requires expertise across multiple technical domains and strong cross-functional collaboration skills to drive innovation and excellence in digital design., * PCB design, including part selection, schematic capture, debug, and optimization * High speed interface design and bring-up and testing, e.g. 100 GigE, Aurora, PCIe * Experience with schematic capture and PCB layout tools, e.g. Allegro, PADS * Familiarity with high speed PCB layout techniques/concepts * Skilled in design techniques that maximize isolation and prevent signal integrity issues. * RTL design (Verilog, VHDL), simulation, timing closure in large FPGAs * Strong communications skills with ability to work in a fast-paced & dynamic environment. * U.S. citizenship * Ability to obtain a Secret Clearance Preferred Education and Experience * Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent experience * 5+ years of relevant experience in digital design engineering * Experience with DOD radar, electronic warfare, or RF communications algorithms * Familiarity with C#, Python, C/C++, TCL * Familiarity with RF systems * Experience with low complexity DC power tree designs and voltage sequencing For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process. ## Description ADI's Aerospace and Defense Sensors, Subsystems, & Space business unit has an open position for an experienced Senior Digital Design Engineer with a background in FPGA/ASIC RTL and schematic capture. Working on new technology development, you will design cutting-edge integrated modules and subsystems for electronic warfare (EW), communication, and phased array radar systems. In this position, you will interface with staff involved with design, testing, manufacturing engineering, program management, business development, and division management throughout all program phases of research, design, and production., * Develop FPGA-based designs for digital data and control paths leveraging ADI high-speed converters, including schematic, RTL, simulation, analysis, and interface validation * Design and implement high speed digital designs for applications in electronic warfare, RF communications, and phased array * Contribute to the architecture and design of FPGA-centric digital hardware, including schematic, RTL, analysis, and interface validation