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# Principal Front-End Design Engineer

- **Company:** Synopsys
- **Location:** Sunnyvale, CA, United States
- **Experience:** Expert
- **Salary:** $191,000.0 - $286,000.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Systems Engineering, Computer Engineering, Software Debugging, Python (Programming Language), SystemVerilog, Tcl (Programming Language), Application Specific Integrated Circuits, Front End Software Development
- **Published:** October 20, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=19dc07f31a4d2b3c

## About the Role

* BS/MS in Electrical Engineering, Computer Engineering, or related field.
 * 10+ years of ASIC, SoC, or IP design and verification experience.
 * Expertise in verification, synthesis, timing constraints, DFT, CDC/RDC, or lint methodologies.
 * Strong experience with Synopsys tools such as VCS, VC SpyGlass, Fusion Compiler, Design Compiler, and TestMAX.
 * Proficient in SystemVerilog, UVM, Tcl, Python, or similar languages.
 * Demonstrated technical leadership and influence across cross-functional engineering teams.

What Sets You Apart

 * Deep understanding of IP reuse, subsystem integration, and SoC development. Passion for
 * ing AI to improve design productivity and quality.
 * Strong problem-solving, communication, and mentoring skills.
 * Ability to translate complex technical challenges into scalable, practical solutions.

## Description

Synopsys is a leader in silicon-to-systems engineering solutions, helping customers accelerate innovation in AI-driven products through industry-leading EDA, IP, and design solutions.
You Are
As a Principal Front-End Design Engineer, you will lead methodology, subsystem architecture, and AI-enabled design innovation across IP and SoC development. You will build scalable design solutions, improve engineering productivity, and drive best practices across global teams.
What You'll Be Doing

 * Develop and deploy AI-driven solutions for verification, synthesis, constraints, and DFT workflows.
 * Architect reusable subsystem reference designs for Synopsys IP.
 * Debug and optimize front-end design methodologies and automation flows.
 * Drive adoption of best practices across design and verification teams.
 * Collaborate with EDA, IP, and customer-facing engineers to solve complex design challenges.
 * Mentor engineers through technical leadership and knowledge sharing.