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# Sr FPGA Design Engineer (NetSec)

- **Company:** Palo Alto Networks
- **Location:** Palo Alto, CA, United States
- **Experience:** Expert
- **Salary:** $156,400 - $253,000
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Automation of Tests, Bash Shell, Boolean Algebra, C++ (Programming Language), Communications Protocols, Cyber Security, Microarchitecture, Software Debugging, Logic Synthesis of Circuits, Perl (Programming Language), Emulators, Ethernet, Formal Verification, Field-Programmable Gate Array (FPGA), Hardware Design, Internet Protocol Security (IP SEC), Internet Security, Python (Programming Language), PCI Express, Rapid Prototyping Process, Static Timing Analysis, SystemVerilog, Systems Integration, Verilog, CPLD, Vivado, Scripting, Application Specific Integrated Circuits, Large Language Models, Hardware Testing, Hardware Acceleration
- **Published:** October 22, 2026
- **Apply:** https://www.careerbuilder.com/job-details/sr-fpga-design-engineer-netsec-palo-alto-ca--84576626-d4a6-4ddd-bc51-88e4fafbdb6d

## About the Role

FPGA Design, Technical/Engineering Design, Leading Edge Technology, Internet Security, Artificial Intelligence (AI), Problem Solving Skills, FPGA, Timing Verification, CPLD, Cross-Functional, * BS in EE, CE, or CS (MSEE or equivalent military experience preferred).

 * 10+ years' front-end ASIC design ownership, shipping 2+ chips to mass production.
 * Expert SystemVerilog and Verilog RTL development skills for FPGA and CPLD architectures.
 * Proven track record of FPGA synthesis, placement, routing, and static timing analysis (STA) closure across multi-clock domains.
 * Scripting proficiency (Python, C/C++, Perl, bash or tcsh).
 * Demonstrated strength in:
 * Integrating and configuring high-speed IP cores (e.g., PCIe Gen4/5/6, QDMA, Ethernet MAC/PHY, memory controllers).
 * FPGA rapid prototyping, in-system logic debugging (ILA, SignalTap), and lab bring-up.
 * Optimizing resource utilization (LUTs, FFs, BRAM/URAM, DSP blocks) and timing closure strategies.
 * Analyzing timing, power, and area reports and driving fixes.
 * Demonstrated proficiency or active experience integrating modern AI tools (e.g., LLM coding assistants, automated test generators, or ML-enhanced EDA features) into hardware design, scripting, or verification workflows.
 * Excellent leadership, collaboration, and written/verbal communication.

Preferred / Nice-to-Have

 * Experience with ASIC-to-FPGA prototyping flows and emulation environments.
 * Hands-on experience with high-density FPGA platforms (AMD UltraScale+, Altera Agilex/Stratix).
 * Formal verification techniques (e.g., VC Formal) applied to FPGA module verification.
 * Networking protocol experience (Ethernet, eDSA, IPsec, packet processing) and CPLD/CFPGA board-management logic design.

## Description

Join our FPGA engineering team and help deliver high-performance digital logic, CPLD/CFPGA modules, and hardware acceleration platforms for our next-generation firewalls. You will own FPGA design from architecture and specification through RTL, timing closure, synthesis, and lab bring-up, collaborating closely with cross-functional software, hardware, and verification teams.

What You'll Do

 * Write comprehensive micro-architecture and functional specifications for FPGA, CFPGA, and CPLD designs.
 * Design high-quality SystemVerilog/Verilog RTL targeted for advanced FPGA architectures (AMD/Xilinx, Altera/Intel) meeting strict timing, power, and area targets.
 * Synthesize & Implement designs using Vivado, Quartus, and Synopsys tools, achieving multi-clock timing closure and resource optimization.
 * Prototype & Validate ASIC designs on FPGA platforms, executing lab bring-up, in-system debugging, and hardware validation.
 * Collaborate with software and platform teams to define interfaces, review memory map structures, and integrate complex IP blocks (PCIe, Ethernet, QDMA, DDR/LPDDR).
 * Innovate: pilot AI-driven design or verification flows that cut schedule risk.