> Markdown version of [/jobs/ext/4346716-senior-vhdl-rtl-digital-logic-engineer](https://www.wearedevelopers.com/jobs/ext/4346716-senior-vhdl-rtl-digital-logic-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

---

# Senior VHDL RTL Digital Logic Engineer

- **Company:** Schweitzer Engineering Laboratories
- **Location:** Pullman, WA, United States
- **Experience:** Expert
- **Salary:** $145,000.0 - $214,000.0
- **Contract:** Permanent contract
- **Skills:** Boolean Algebra, C++ (Programming Language), Logic Synthesis of Circuits, Microprocessors, Ethernet, Firmware, Field-Programmable Gate Array (FPGA), Static Timing Analysis, Verilog, VHSIC Hardware Description Language (VHDL), IEEE 802.3
- **Published:** October 22, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=e25cc63b9717cb95

## About the Role

* are passionate about designing RTL digital logic for FPGAs.
 * enjoy solving difficult problems with efficient and creative solutions.
 * have experience in both RTL, hardware and firmware development practices.
 * are knowledgeable in networking/Ethernet (IEEE 802.3) and precise timing technologies such as PTP (IEEE 1588) and IRIG-B.
 * want a career making electric power safer, more reliable, and more economical., * B.S. degree in Electrical Engineering, related discipline, or equivalent combination of education and experience
 * 8+ years of combined experience in at least 2 of the following areas:
 + RTL Digital Design with FPGAs using VHDL/Verilog
 + Xilinx, Intel FPGA (Altera), Microchip (Microsemi/Actel), Lattice Semiconductor Tools
 + Firmware Design with FPGA SOCs/Microprocessors using C/C++
 + Simulation, Synthesis and Timing Analysis of Digital Logic
 + Functional verification of RTL Digital Logic
 * Ability to work cooperatively in a team environment
 * Ability to rapidly learn new skills and assume new responsibilities
 * Ability to mentor others
 * Strong writing, technical documentation and speaking
 * Background check results satisfactory to SEL
 * Negative drug test result(s)

Preferred Qualifications

 * Supervisory experience or training
 * Strong project management knowledge and skills

## Description

* Serving as technical lead on complex VHDL RTL digital logic projects.
 * Creating and maintaining internal RTL design documentation.
 * Writing test plans and developing test harnesses/stimulus for RTL functional verification.
 * Preparing design and system level specifications.
 * Participating or moderating peer reviews of designs, documentation and test plans.
 * Providing and maintaining accurate project plans and labor estimates.
 * Working closely with product managers on new product concepts and enhancements.
 * Engaging with cross-discipline teams to deliver world-class products for critical infrastructure.