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# Hardware Engineer II - Design Verification

- **Company:** HPR Partners LLC
- **Location:** Boston, MA, United States
- **Experience:** Experienced
- **Salary:** $90,000 - $216,000
- **Contract:** Permanent contract
- **Skills:** C (Programming Language), Adobe InDesign, Computer Engineering, Software Debugging, Linux, Logic Synthesis of Circuits, Perl (Programming Language), Ethernet, Formal Verification, Field-Programmable Gate Array (FPGA), Python (Programming Language), Network Protocols, PCI Express, Specman, SystemVerilog, Transmission Control Protocol (TCP), Scripting, Computer Networking Systems, Information Technology
- **Published:** October 27, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=1c957fa10079b3b4

## About the Role

* BS/MS in Computer Engineering, Electrical Engineering, Computer Science, or related field
 * 2+ years of experience in design verification for FPGAs or ASICs
 * Proficiency in SystemVerilog for verification
 * Familiarity with verification methodologies, including constrained randomization, functional coverage, and assertion-based checking
 * Experience with simulation and debugging tools (e.g., VCS, Verdi)
 * Comfortable working in a Linux environment
 * Strong problem-solving, debugging, and communication skills, * Experience developing and debugging UVM-based verification environments and testbenches using SystemVerilog
 * Understanding of computer architecture and digital design concepts
 * Knowledge of networking protocols (IP, TCP, UDP)
 * Experience verifying designs with high-speed interfaces (PCIe, Ethernet, and/or DDR)
 * Familiarity with C programming and scripting in Python and/or Perl

## Description

* Verify and maintain high-performance FPGA compute and networking systems used in electronic trading
 * Contribute to the verification process from specification, test planning, and testbench development through execution and coverage closure
 * Partner with design engineers to develop, review, and execute comprehensive test plans
 * Create and maintain reusable verification components and testbenches written in SystemVerilog
 * Utilize simulation and debugging tools to identify, investigate, and resolve design issues
 * Contribute to improving our verification processes, tools, and methodologies