> Markdown version of [/jobs/ext/4402019-rtl-design-engineer-machine-learning-accelerators](https://www.wearedevelopers.com/jobs/ext/4402019-rtl-design-engineer-machine-learning-accelerators). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # RTL Design Engineer, Machine Learning Accelerators - **Company:** Google LLC - **Location:** Sunnyvale, CA, United States - **Experience:** Experienced - **Salary:** $138,000.0 - $197,000.0 - **Contract:** Permanent contract - **Skills:** Code Review, Computer Engineering, Perl (Programming Language), Python (Programming Language), Machine Learning, CPU Design, SystemVerilog, Verilog, Scripting, Application Specific Integrated Circuits, Information Technology, Code Restructuring - **Published:** October 5, 2026 - **Apply:** https://dejobs.org/x/x/CFE8698338C34F65B6B44495A565D802/job/ ## About the Role Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area., * Bachelor's degree in electrical engineering, computer engineering, computer science, or a related field, or equivalent practical experience. * 4 years of experience with custom silicon design (e.g., SoCs, ASICs, etc.). * Experience with RTL design using Verilog or SystemVerilog., * Master's degree or PhD in electrical engineering, computer engineering, or computer science, with a focus on computer architecture. * Experience interacting with software, architecture, and other cross-functional teams. * Experience with a scripting language (e.g., Python or Perl). * Experience applying engineering best practices (e.g., code review, testing, refactoring). * Knowledge of processor design, accelerators, or memory hierarchies and machine learning algorithms. * Knowledge of high performance and low power design techniques. ## Description * Understand the overall application of the chip, proposing and developing improvements in overall design. * Design and document one or more blocks of an ASIC, including functionality and timing. * Work with software teams on functionality, interfaces, and documentation.