> Markdown version of [/jobs/ext/4409815-fpga-engineer](https://www.wearedevelopers.com/jobs/ext/4409815-fpga-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # FPGA Engineer - **Company:** QuEST Defense - **Location:** Tucson, AZ, United States - **Experience:** Expert - **Salary:** $145,000.0 - $185,000.0 - **Contract:** Permanent contract - **Skills:** Code Coverage, Software Debugging, Logic Synthesis of Circuits, Field-Programmable Gate Array (FPGA), SystemVerilog, VHSIC Hardware Description Language (VHDL), Physical Design - **Published:** October 20, 2026 - **Apply:** https://www.indeed.com/viewjob?jk=e948ef01f7837a6a ## About the Role We're seeking engineers who thrive on solving hard problems and turning bold ideas into real-world solutions. If you're driven to design, develop, and test technology that truly makes an impact, you'll feel at home here., FPGA Engineer - Mid-Level * Minimum 5 years' experience including at least one of: + Digital design & VHDL coding + Xilinx or Microsemi device/tools experience + Delivering FPGA solutions to system-level applications + Hands-on integration & debug FPGA Engineer - Senior/Principal Level * Minimum 8 years of experience including at least one of the above areas. * Ability to support complex design efforts from concept through production. * Experience of collaborating with multidisciplinary engineering teams., * Experience in radar or image processing (RF/EO). * Embedded systems design using ARM, Microblaze, or Nios processors. * Experience with gigabit serial interfaces and multi-gigabit transceivers (MGTs). * UVM/System Verilog-based constrained-random verification. * Verification using emulation platforms such as Veloce. ## Description * Architect FPGA-based systems, determining interfaces, device selection, and concept of operations (CONOPS). * Translate system-level requirements into FPGA requirements. * Design and code FPGA implementations in VHDL with emphasis on reliability and maintainability. * Perform simulation, place-and-route, and verification using both directed tests and constrained-random techniques. * Track functional and code coverage during verification. * Integrate and debug designs in lab environments. * Deliver production-quality FPGA releases from prototype through full production. * Create detailed documentation: requirements, verification plans, user guides. * Support internal and external technical reviews.