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# ASIC DFT Engineer

- **Company:** Cisco Systems, Inc.
- **Location:** Austin, TX, United States
- **Experience:** Expert
- **Salary:** $139,300.0 - $203,600.0
- **Contract:** Permanent contract
- **Skills:** Computer-Aided Design, Computer Engineering, Software Debugging, Electronic Design Automation, Joint Test Action (IEEE Standards), Verilog, Application Specific Integrated Circuits, Backend, Front End Software Development, Physical Design
- **Published:** October 26, 2026
- **Apply:** https://www.juju.com/job/1_cisco2-2018241

## About the Role

You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities. **Minimum Qualifications:** + Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 7 years of experience. + Prior experience working in the latest innovative trends in DFT, test and silicon engineering. + Prior experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. + Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime + Prior experience working with Gate level simulation, debugging with VCS and other simulators. + Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 **Preferred Qualifications:** + Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verification + DFT CAD

## Description

Our innovations in silicon, optics, and hardware platforms-like Silicon One-are shaping the technology industry.
We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow.
Because full product development-from design to qualification to production-is within our team, we're able to think differently, experiment more, and work quickly.
Join us to power the future of the digital world. **Your Impact:** You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle.
As a member of this team you will also be involved in crafting groundbreaking next generation networking chips.