> Markdown version of [/jobs/ext/4426980-senior-fpga-engineer](https://www.wearedevelopers.com/jobs/ext/4426980-senior-fpga-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

---

# Senior FPGA Engineer

- **Company:** FieldLine Medical
- **Location:** Louisville, CO, United States
- **Experience:** Expert
- **Salary:** $130,000.0 - $165,000.0
- **Contract:** Permanent contract
- **Skills:** C++ (Programming Language), Computer Engineering, Data Recovery, Software Debugging, Embedded Software, Field-Programmable Gate Array (FPGA), System on a Chip, SystemVerilog, Git Flow
- **Published:** October 6, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=442cff14b5d1ddc7

## About the Role

* B.S. in Electrical Engineering, Computer Engineering, or a closely related field; M.S. preferred
 * 7+ years of professional FPGA design experience, with a track record of owning a subsystem end to end
 * Experience with SystemVerilog
 * Hands-on experience designing and debugging high-speed serial transceivers (SerDes, multi-gigabit links, clock/data recovery, equalization, jitter and eye-diagram work)
 * Practical DDR4 experience: controller integration, calibration, timing closure, and real-world throughput debugging
 * Strong lab and debug skills
 * Self-directed and independent with a willingness to learn on the go
 * Ability to work on-site in Louisville, CO

Nice to Have

 * Experience with Intel/Altera FPGAs, particularly Arria 10
 * Experience with Efinix FPGAs (Trion T20)
 * DSP and control-systems background - digital filters, feedback loops, closed-loop sensor control
 * C++ and System-on-Chip development, including Arria 10 HPS or similar hard-processor integration
 * Experience in a regulated medical device environment (ISO 13485, IEC 62304, design controls, V&V documentation)
 * Familiarity with Git-based workflows

## Description

We are looking for a Senior FPGA Engineer to improve upon the existing HEDscan FPGA architecture, help design the next-generation HEDscan system, design, verify, and implement new accessory cards for our platform. You will own FPGA subsystems end to end - from architecture through verification - working at the hardware/software boundary to keep our systems fast, stable, and reliable., * Architect, implement, and verify FPGA designs for our HEDscan system

 * Design and implement high-speed serial transceiver links between HEDscan chassis
 * Design and incorporate DDR4 memory on the System on Module
 * Improve existing real-time control and DSP data paths (filtering, decimation, feedback loops) that keep the sensor array stable
 * Drive timing closure, resource budgeting, and design-for-test across Arria 10 devices
 * Build simulation and verification environments
 * Partner with embedded software on the hardware/software boundary, register maps, DMA, and SoC integration
 * Contribute to design documentation and verification evidence within our ISO 13485 design control process
 * Participate in on-site testing and measurements using the HEDscan system