> Markdown version of [/jobs/ext/4440655-gpu-pcie-and-boot-architect](https://www.wearedevelopers.com/jobs/ext/4440655-gpu-pcie-and-boot-architect). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # GPU PCIe and Boot Architect - **Company:** G P U Nuclear, Inc - **Location:** United States - **Salary:** $108,000.0 - $178,250.0 - **Contract:** Internship / Graduate position - **Skills:** C++ (Programming Language), Perl (Programming Language), PCI Express, Software Construction, Subsystems, Systems Architecture, Scripting, Graphics Processing Unit (GPU), Performance Testing, Information Technology - **Published:** October 7, 2026 - **Apply:** https://startup.jobs/gpu-pcie-and-boot-architect-new-college-grad-2027-2100-nvidia-usa-10313693 ## About the Role * Pursuing or recently completed a BS or MS in Computer Architecture, Computer Science, or Electrical Engineering (or related degree) or equivalent experience * Coursework in Computer Architecture, Operation systems, and/or system architecture * Experience with HW/SW interactions * Experience building software models, diagnostic tests, and/or directed function and performance tests. * Strong Proficiency in C++ (previous project or internship experience is preferred) Ways to stand out from the crowd: * Knowledge of Advanced interconnects (PCIe, AXI, nvlink, or similar) * Experience with scripting languages such as Perl * Understanding of modern security constructs and/or encryption * Knowledge of RiscV architecture and microcode development ## Description * As a member of the architecture team, you will be responsible for understanding how the GPU sub-system modules interoperate and interact with overall system * You will architect and plan features in concert with software, hardware, and verification teams across the globe to implement the next iteration of GPUs * Create functional and performance models, often in C++, along with test plans to validate the features you design * Actively support post-silicon validation activities