> Markdown version of [/jobs/ext/4454810-field-programmable-gate-array-engineer](https://www.wearedevelopers.com/jobs/ext/4454810-field-programmable-gate-array-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

---

# Field Programmable Gate Array Engineer

- **Company:** EXCEL DELIVERY SYSTEMS
- **Location:** Cedar Rapids, IA, United States
- **Experience:** Experienced
- **Salary:** $145,600.0 - $187,200.0
- **Contract:** Permanent contract
- **Skills:** Software Debugging, Digital Electronics, Field-Programmable Gate Array (FPGA), Static Timing Analysis, Subversion, Toolchain, Verilog, VHSIC Hardware Description Language (VHDL), Vivado, Application Specific Integrated Circuits, Fpga Hardware, Git, Software Version Control
- **Published:** October 19, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=a70639d4178b225f

## About the Role

· Must have active secret clearance

· Must have some fpga design experience

Qualifications You Must Have

 * Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 5 years prior relevant experience or an Advanced Degree in a related field and minimum 3 years of experience.
 * An active U.S. government issued Final Secret Security Clearance is required
 * A minimum of 3 years professional experience in FPGA development, ASIC front end, or related areas
 * Proficient in VHDL/Verilog for FPGA/ASIC design and implementation.
 * Experience in digital circuit architecture, design, resource tradeoffs, timing analysis, and timing closure
 * Familiarity with FPGA platforms such as AMD/Xilinx, Altera, Microchip, or others, and associated toolchains (e.g., Vivado, Quartus, Libero).
 * Strong debugging and troubleshooting skills for FPGA/ASIC systems.
 * Proficiency with revision control concepts and tools (e.g., Git, Subversion)