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# Sr Principal Software Engineer, Innovus - Physical Synthesis & Optimization

- **Company:** Cadence Design Systems, Inc.
- **Location:** San Jose, United States
- **Experience:** Expert
- **Salary:** $161,000.0 - $299,000.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Algorithm Design, Unit Testing, C++ (Programming Language), Nvidia CUDA, Computer Engineering, Concurrent Computing, Data Structures, Software Debugging, Distributed Systems, Memory Management, Electronic Design Automation, Python (Programming Language), Linux System Administration, Machine Learning, Multiprocessing, Software Architecture, Computational Geometry, Shell Script, Software Systems, Spatial Data Infrastructures, Static Timing Analysis, Tcl (Programming Language), Reinforcement Learning, Multithreading, Scripting, Deep Learning, Information Technology, Data Analytics, Physical Design, Vectorization
- **Published:** October 1, 2026
- **Apply:** https://startup.jobs/sr-principal-software-engineer-innovus-physical-synthesis-optimization-secure-ic-france-10242995

## About the Role

Required

 * Education: Master's or Ph.D. in Computer Science, Electrical Engineering, Computer Engineering, or a related quantitative field (or equivalent hands-on industry experience).
 * C++ Expertise: Strong hands-on experience developing high-performance, production-quality C++ (C++17/20) in Linux environments.
 * Core Fundamentals: Solid foundation in data structures, graph algorithms, computational geometry, memory management, and software architecture.
 * Concurrent Programming: Practical experience with multithreaded or concurrent programming and low-level performance profiling.
 * Problem Solving: Proven ability to analyze, debug, and optimize complex algorithmic bottlenecks in large-scale software systems.

Preferred

 * EDA / Physical Design: Prior experience developing EDA tools, with specific knowledge in physical synthesis, global/detail placement, static timing analysis (STA), routing, or timing closure.
 * AI & Machine Learning: Exposure to applying machine learning, deep learning, reinforcement learning, or data-driven heuristics to software optimization problems.
 * Scripting & Tooling: Proficiency with Python, Tcl, or shell scripting for benchmarking and workflow automation.
 * HPC & Acceleration: Experience with SIMD vectorization, GPU/CUDA acceleration, or large-scale distributed compute frameworks., This role is ideal for a hands-on developer who loves tackling hard algorithmic and systems-level problems at massive scale. Whether your background is rooted deeply in EDA or high-performance systems C++, you will directly write the foundational software engines that power the next generation of global silicon innovation.

## Description

In this hands-on engineering role, you will solve challenging computational problems at the intersection of advanced graph/spatial algorithms, high-performance C++, parallel and distributed computing, and large-scale numerical optimization. Your work will operate at semiconductor scale-where algorithmic efficiency, memory footprint, and multi-core scalability directly impact the ability to design billions of transistors on advanced process nodes., Core Engine & Algorithm Development

 * Design, implement, unit-test, and optimize high-performance C++ engines for physical synthesis, placement, and timing-driven optimization.
 * Develop advanced graph algorithms, spatial data structures, and continuous/combinatorial optimization techniques for massive-scale physical design workloads.
 * Identify and eliminate CPU bottlenecks, memory footprint overhead, and algorithmic scaling limits in production C++ codebases.
 * Translate research concepts and mathematical formulations into robust, maintainable, production-quality software.

Parallel & Distributed Computing

 * Implement multi-threaded and distributed algorithms for computationally intensive implementation engines.
 * Scale physical design workloads across multi-core systems and compute clusters while minimizing synchronization overhead and memory bandwidth constraints.
 * Apply modern profiling and benchmarking tools to maximize CPU utilization, cache efficiency, and execution throughput.

Physical Design Optimization & R&D

 * Develop physical design optimization modules addressing timing, power, performance, area (PPA), and congestion.
 * Work directly with large-scale layout and netlist data to build practical, highly scalable optimization strategies.
 * Collaborate with R&D colleagues to integrate data-driven and AI-assisted optimization heuristics into core synthesis flows.