> Markdown version of [/jobs/ext/4476485-asic-verification-engineer-ring-blink-asic-team](https://www.wearedevelopers.com/jobs/ext/4476485-asic-verification-engineer-ring-blink-asic-team). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # ASIC Verification Engineer, Ring/Blink ASIC Team - **Company:** Amazon.com, Inc. - **Location:** North Reading, MA, United States - **Salary:** $153,600.0 - $215,000.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Software Debugging, Perl (Programming Language), Emulators, Field-Programmable Gate Array (FPGA), Python (Programming Language), Verification and Validation (Software), System Testing, Video Editing, Scripting, Application Specific Integrated Circuits - **Published:** October 12, 2026 - **Apply:** https://www.jobmonkeyjobs.com/career/28101813/Asic-Verification-Engineer-Ring-Blink-Asic-Team-Massachusetts-North-Reading-7375 ## About the Role Bachelor's degree in Electrical Engineering or a related field - Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills - Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing, Master's degree in Electrical or Communications Engineering or a related field - Experience working with high-performance industry standard buses like AMBA AXI4 - Experience with industry standard tools and scripting languages (Python or Perl) for automation - Experience using multiple verification platforms: UVM test bench, FPGA, emulator, software environments, and system testing ## Description Join the team that delivers highly differentiated silicon powering Blink and Ring battery-powered devices. Our verification team operates on state-of-the-art SoCs within a vertically integrated environment, contributing to early architectural and micro-architectural trade-offs that reduce time-to-revenue by compressing the DV cycle. In this role you will use bit-accurate C reference models as golden baselines to verify image and video processing subsystems, build and maintain UVM-based testbench environments with automated stimulus generation and scoreboarding, and drive gate-level simulations to ensure timing-accurate, power-aware signoff. Our integrated verification and validation flow spans architectural modeling through post-silicon bring-up - giving engineers end-to-end visibility into the designs they verify. The team works backwards from customer requirements to deliver ultra-low-power, energy-efficient products incorporating the latest in AI, video processing, low-power communications, and advanced CMOS fabrication technology. Key job responsibilities - Use and/or build bit accurate C models - Evaluate block and sub-systems for testability/verifiability - Write and execute comprehensive block and system level testplans - Build assertions, traffic generators and scoreboards - Build and assess RTL coverage metrics