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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Software Engineer - High-Speed SerDes - **Company:** Eridu Corporation - **Location:** Saratoga, CA, United States - **Experience:** Expert - **Contract:** Permanent contract - **Skills:** Testing (Software), Abstraction Layers, Application Programming Interfaces (APIs), Data Analysis, C++ (Programming Language), Command-Line Interface, Content Management Interoperability Services, Computer Networks, Computer Engineering, Data Recovery, Software Debugging, Embedded Software, Ethernet, Firmware, Field-Programmable Gate Array (FPGA), Python (Programming Language), PCI Express, Software Architecture, Software Maintenance, Software Engineering, System Software, IEEE 802.3, Network Switches, PIC Microcontroller, Application Specific Integrated Circuits, Information Technology - **Published:** October 27, 2026 - **Apply:** https://www.careerbuilder.com/job-details/software-engineer-high-speed-serdes-saratoga-ca--4e50fd1b-7878-4df9-a382-71e5344c2b3d ## About the Role Software Engineering, SERDES, Ethernet, Software Engineering, SERDES, PCI Express (PCI-E), Computer Networks, PHY, Equalization, Printed Circuit Board Design, * Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. * Typically 10 or more years of experience in SerDes firmware, PHY software, silicon bring-up, or high-speed interface validation. * Deep understanding of high-speed serial-link fundamentals, including: * + PAM4 and NRZ signaling + Channel loss, insertion loss, and return loss + Jitter, noise, crosstalk, and reflections + Clock and data recovery + Transmitter feed-forward equalization + CTLE and decision-feedback equalization + BER, eye diagrams, and link margin + Forward error correction * Hands-on experience bringing up and debugging at least one advanced SerDes generation, preferably 112G or 224G PAM4. * Strong experience with one or more of the following: * + Ethernet SerDes and IEEE 802.3 link training + PCIe Gen5, Gen6, or later-generation PHYs + UCIe or another high-speed die-to-die interface * Strong embedded programming skills in C and C++. * Experience with Python or similar languages for automation, characterization, data analysis, and laboratory equipment control. * Experience programming SerDes registers through MDIO, I²C, SPI, PCIe configuration space, memory-mapped registers, or vendor-specific interfaces. * Familiarity with embedded processors, microcontrollers, real-time firmware, interrupts, DMA, and hardware/software interfaces. * Experience debugging pre-silicon models, emulation platforms, FPGA prototypes, and post-silicon devices. * Ability to interpret schematics, package and board topology, channel models, IBIS-AMI results, and signal-integrity reports. * Experience using laboratory equipment such as high-bandwidth oscilloscopes, BERTs, VNAs, protocol analyzers, and traffic generators. * Strong root-cause analysis skills and the ability to debug complex issues spanning analog, digital, firmware, package, board, and system domains., * Experience with 224G-per-lane Ethernet PHYs and 800G, 1.6T, or higher-speed Ethernet systems. * Experience with PCIe 6.x or PCIe 7.0, including PAM4 signaling, FLIT mode, FEC, and lane margining. * Experience with UCIe PHY and adapter-layer bring-up in multi-die or chiplet-based systems. * Familiarity with long-reach, medium-reach, short-reach, very-short-reach, and die-to-die SerDes channels. * Experience integrating third-party SerDes IP into an ASIC or SoC. * Experience developing vendor-independent SerDes abstraction layers. * Knowledge of CMIS, pluggable optics, retimers, active electrical cables, and linear-drive optics. * Familiarity with IEEE 802.3, PCI-SIG, and UCIe Consortium specifications. * Experience with SerDes power optimization, fast link recovery, degradation detection, and field diagnostics. * Experience developing production screening, yield-analysis, and manufacturing-test solutions. * Experience working with advanced process nodes, 2.5D packaging, interposers, and chiplet-based architectures. * Track record of technical leadership, cross-functional execution, and mentoring. ## Description We are seeking a highly experienced SerDes software engineer to lead the development, bring-up, validation, and optimization of next-generation high-speed interfaces. The successful candidate will work with 224 Gb/s-per-lane Ethernet SerDes, PCI Express, and UCIe chiplet interconnects in advanced networking and compute silicon., This is a senior technical role requiring strong knowledge of SerDes architecture, PHY initialization, link training, equalization, calibration, diagnostics, and system-level signal-integrity behavior. The engineer will work closely with analog and mixed-signal designers, ASIC architects, firmware teams, validation engineers, board designers, and system software developers., * Develop embedded software and firmware for configuring, initializing, calibrating, and monitoring high-speed SerDes PHYs. * Lead bring-up and optimization of 224G PAM4 SerDes used in Ethernet switch, networking, and accelerator products. * Develop software support for PCIe SerDes, including link initialization, training, equalization, lane management, error recovery, and diagnostics. * Develop software support for UCIe die-to-die interfaces, including PHY initialization, link training, lane repair, health monitoring, and failure analysis. * Implement SerDes adaptation and calibration workflows, including: * + Transmitter amplitude, pre-cursor, and post-cursor tuning + Receiver CTLE, VGA, DFE, and CDR configuration + Adaptive equalization + Eye optimization and margining + Lane-to-lane skew management + Polarity inversion and lane remapping + Background calibration and environmental compensation * Develop APIs, drivers, firmware interfaces, command-line tools, and diagnostic utilities for SerDes control. * Support Ethernet auto-negotiation and link training, including Clause 73 and Clause 72/136-related workflows where applicable. * Support PCIe LTSSM interaction, preset and coefficient negotiation, lane margining, retraining, and recovery. * Support UCIe link state management, PHY repair mechanisms, sideband interactions, and link reliability features. * Create automated characterization and production-test software for: * + PRBS generation and checking + BER measurement + Eye scans and bathtub curves + Jitter and signal-margin analysis + Loopback testing + Lane failure isolation + Channel and package characterization * Analyze difficult link failures across silicon, package, board, connector, cable, and optical-module channels. * Correlate software-visible SerDes telemetry with oscilloscope, BERT, VNA, and simulation results. * Develop algorithms and policies for runtime SerDes health monitoring, telemetry, predictive failure detection, and fault recovery. * Optimize SerDes performance across process, voltage, temperature, channel loss, and manufacturing variation. * Define software architecture and reusable abstractions that support multiple SerDes IP vendors and PHY generations. * Create technical specifications, programming guides, bring-up procedures, debug playbooks, and validation plans. * Mentor engineers and serve as the organization's technical authority for SerDes software and system bring-up., * Establish stable links across challenging channels and operating conditions. * Convert low-level SerDes capabilities into robust, maintainable software. * Provide actionable diagnostics rather than opaque link-up or link-down status. * Reduce silicon bring-up and customer-debug time through automation and strong observability. * Build a reusable SerDes software architecture spanning Ethernet, PCIe, UCIe, and future high-speed interfaces. Role Scope This position focuses on SerDes control software, embedded firmware, link management, diagnostics, characterization, and system-level optimization. It will work closely with-but does not replace-the analog/mixed-signal SerDescircuit-design function.