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# Design for Test (DFT) Engineer

- **Company:** Voltai Inc.
- **Location:** Palo Alto, CA, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Build Automation, Software Debugging, Tcl (Programming Language), Strategies of Testing, Scripting, Physical Design
- **Published:** October 22, 2026
- **Apply:** https://www.juju.com/job/16_3f6fadd8

## About the Role

* 5+ years of DFT experience on production tapeouts.
 * Hands-on experience with Tessent, TestMAX, or Modus.
 * Strong knowledge of scan, compression, ATPG, MBIST, and IEEE 1149.1/1687.
 * Experience with DFT verification and gate-level simulation.
 * Tcl and Python scripting.

Bonus Points

 * Post-silicon test bring-up and ATE experience.
 * Experience with 2.5D/3D or chiplet test strategies.
 * Interest in AI-assisted design tools.

## Description

You'll make sure the chips we work on can be tested in manufacturing and in the field. You'll own DFT architecture and implementation on real silicon programs with leading semiconductor companies while helping Voltai's AI learn DFT methodology.

What You'll Do

 * Define DFT architecture for SoCs and IP, including scan, compression, MBIST, LBIST, and boundary scan.
 * Insert and verify DFT logic, and generate ATPG patterns that meet coverage targets.
 * Work with RTL, synthesis, and physical design teams to close DFT timing and area impact.
 * Support silicon bring-up, pattern debug, and yield analysis with test and product engineering.
 * Build automation for DFT flows and coverage reporting.
 * Help define how AI can accelerate DFT insertion and pattern generation.