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# RTL Design Engineer

- **Company:** Voltai Inc.
- **Location:** Palo Alto, CA, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Microarchitecture, Software Debugging, Ethernet, Formal Verification, Python (Programming Language), PCI Express, Subsystems, SystemVerilog, Tcl (Programming Language), Verilog, Backend
- **Published:** October 22, 2026
- **Apply:** https://www.juju.com/job/15_d26a4a28

## About the Role

* 5+ years of RTL design experience on chips that taped out.
 * Expert SystemVerilog/Verilog and strong microarchitecture skills.
 * Hands-on experience with lint, CDC, synthesis, and timing-aware design.
 * Familiarity with common protocols (AXI, PCIe, Ethernet, DDR, or similar).
 * Python or Tcl scripting.

Bonus Points

 * Experience writing SVA or working with formal verification.
 * Low-power design (UPF, clock and power gating).
 * Interest in AI-assisted design tools.

## Description

* Own microarchitecture and RTL implementation for IP blocks and subsystems in SystemVerilog.
 * Drive designs through lint, CDC/RDC, synthesis, and timing closure with the backend team.
 * Partner with verification and formal teams on test plans, assertions, and coverage closure.
 * Debug complex functional and timing issues across simulation, emulation, and silicon.
 * Review and evaluate AI-generated RTL, and help define what correct, high-quality design looks like.
 * Work directly with customer design teams when needed.