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# SR ASIC Design Engineer - NoC & AXI Interconnect

- **Company:** Advanced Micro Devices, Inc.
- **Location:** Santa Clara, CA, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Computer Engineering, Perl (Programming Language), Design of User Interfaces, Python (Programming Language), Queue Management Systems, Shell Script, SystemVerilog, Verilog, Network Switches, Computer Network Operations, Application Specific Integrated Circuits, Front End Software Development, Physical Design
- **Published:** October 31, 2026
- **Apply:** https://www.careerbuilder.com/job-details/sr-asic-design-engineer-noc-axi-interconnect-santa-clara-ca--2e8f1bda-664f-4013-83fd-3b43bde2b440

## About the Role

Technical/Engineering Design, ASIC Design, Team Player, Gaming, Network Operations Center, Embedded Systems, Artificial Intelligence (AI), Product Development, ASIC (Application Specific Integrated Circuit), User Interface Design, * Understanding of Network-on-Chip (NoC) architecture, protocols, and design

 * Experience with AXI, ACE, and APB interface design and verification
 * Knowledge of queuing system design and buffer management
 * Experience with VCS simulation tool, Perl/Python/Shell scripting, and SystemVerilog/Verilog RTL design

ACADEMIC CREDENTIALS:

 * Bachelors or Masters degree in computer engineering/Electrical Engineering

## Description

You will contribute to the ASIC (chip) design for high-performance network chips: AINIC and DPU. As a member of the NTSG ASIC Design Team, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

THE PERSON:

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

 * Network-on-Chip (NoC) design and integration
 * AXI, ACE, and APB interface design and verification
 * Queuing system design and implementation
 * Collaboration with architecture, IP, and physical design teams for first-pass silicon success
 * Post-silicon bring-up support and yield learning, AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.