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# Helix AI Engineer, Training Performance

- **Company:** FIGURE, INC.
- **Location:** San Jose, CA, United States
- **Experience:** Experienced
- **Salary:** $200,000.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, C++ (Programming Language), Profiling, Nvidia CUDA, Computer Programming, Computer Networks, Extract Transform Load (ETL), Software Debugging, Fault Tolerance, InfiniBand, Python (Programming Language), Open Source Technology, Performance Tuning, Remote Direct Memory Access, Regression Testing, Graphics Processing Unit (GPU), Pytorch, DeepSpeed, AWS Trainium, Information Technology, Performance Monitor, Machine Learning Operations, Mixed Precision, VLLM, Megatron
- **Published:** November 3, 2026
- **Apply:** https://www.careerbuilder.com/job-details/helix-ai-engineer-training-performance-san-jose-ca--14bb9d6c-b1b4-4b10-a8d2-acb96584a478

## About the Role

Artificial Intelligence (AI), Robotics, Artificial Intelligence (AI), Human Intelligence (HUMINT), Performance Engineering, Kernel Programming, GPU (Graphics Processing Unit), Topology, Purchasing/Procurement, CUDA (Compute Unified Device Architecture), * Bachelor's or Master's degree in Computer Science, Computer/Electrical Engineering, or a related field.

 * 3+ years in AI performance engineering, with significant time leading large-scale performance improvement projects.
 * Deep understanding of GPU architecture and performance characteristics (memory bandwidth, compute-bound vs. memory-bound ops, occupancy).
 * Proficiency with profiling tools (Nsight Systems/Compute, PyTorch Profiler, HTA, or similar) and ability to translate traces into concrete optimizations.
 * Solid grasp of collective communication (NCCL) and modern networking concepts (RDMA, NVLink, InfiniBand/RoCE, topology-aware placement).
 * Strong Python and CUDA/C++ skills; comfortable reading and modifying framework internals.
 * Experience debugging performance regressions and instability at scale (stragglers, hangs, OOMs, numerical divergence).
 * Experience defining and reasoning about hardware-efficiency metrics (MFU/HFU) and using them to drive optimization priorities.

Bonus Qualifications:

 * Experience with heterogeneous or multi-datacenter training setups and cross-cluster orchestration.
 * Contributions to open-source ML systems projects (PyTorch, Megatron-LM, vLLM, DeepSpeed, JAX, etc.).
 * Exposure to non-NVIDIA accelerators (AMD GPUs, TPU/Trainium/Inferentia, or custom silicon) and heterogeneous fleet management.

## Description

Figure's vision is to deploy autonomous humanoids at a global scale. Our Helix team is looking for an experienced AI Training Performance Engineer to take our model training to the next level. This role is focused on improving distributed training frameworks for large scale model training, optimizing GPU kernels, exploring the relative gains of different accelerator types and co-designing our models to maximize utilization of our hardware., * Optimize training performance for a 100B+ parameter models across 100k+ GPUs.

 * Collaborate with the broader team on accelerator choice, cluster topology, scheduling, and hardware procurement decisions to inform future scaling.
 * Write and optimize custom kernels (Triton/CUDA).
 * Build tooling and dashboards for continuous performance monitoring, regression detection, and root-cause analysis across training jobs.
 * Optimize data loading and preprocessing pipelines so I/O never gates the accelerators.
 * Improve checkpointing, fault tolerance, and elastic restart so large jobs recover quickly from node failures without losing significant wall-clock time.
 * Partner with researchers to co-design model architectures and training recipes that are performant at scale (e.g., activation checkpointing strategies, mixed precision, sequence packing).
 * Extend and contribute to kernel compilers (e.g., Triton, Gluon) to improve iteration speed and enable targeting of custom/non-NVIDIA accelerators.
 * Build and extend agentic systems that automatically generate, benchmark, and iterate on custom kernels.
 * Evaluate emerging accelerator architectures (AMD, TPU, SRAM-based ASICs, and other novel hardware) for fit with our training workloads, and lead proof-of-concept ports/benchmarks.
 * Explore different model/data parallelisms (FSDP, context parallel, expert parallel, etc.) to determine optimal configuration per model size.