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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Principal Digital Design Engineer - **Company:** Powerlattice Technologies Incorporated - **Location:** Chandler, AZ, United States - **Experience:** Expert - **Salary:** $200,000.0 - $250,000.0 - **Contract:** Permanent contract - **Skills:** Code Coverage, Computer Engineering, Software Debugging, Logic Synthesis of Circuits, Digital Technology, Electronic Design Automation, Firmware, Formal Verification, Static Timing Analysis, Backend, Front End Software Development, Physical Design - **Published:** June 3, 2026 - **Apply:** https://www.indeed.com/viewjob?jk=949e308843e7695f ## About the Role Do you have experience in Digital circuit design?, Do you have a Master's degree?, This is a Hybrid role requiring 3 days a week onsite at our HQ's in Vancouver, WA (Greater Portland Area) or Chandler, AZ. While we are primarily seeking candidates in HQ-Vancouer and Chandler, remote flexibility may be considered for exceptional candidates in Silicon Valley, CA. * Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field * 10+ years of experience in digital design with significant hands-on RTL development * Proven track record of delivering complex SoC or subsystem designs to tapeout * Strong expertise in: + RTL design and microarchitecture + SoC integration and standard interfaces * Hands-on experience with back-end flows, including: + Scan insertion and DFT (scan, MBIST, test coverage) + Logic equivalence checking (LEC) + Static timing analysis (STA) and timing closure + Timing constraint development and debug (SDC) * Solid understanding of: + Clocking, resets, CDC/RDC, and low-power design + Synthesis and physical design implications * Experience with industry-standard EDA tools (Synopsys, Cadence) * Experience with low-power methodologies (UPF/CPF) * Strong debugging and problem-solving skills, * Familiarity with advanced technology nodes and implementation challenges * Experience with formal verification techniques * Experience with silicon bring-up and post-silicon debug ## Description We are seeking a highly skilled and hands-on Principal Digital Design Engineer to drive the microarchitecture, design, and implementation of complex digital systems and SoC components. This role combines deep technical contribution with team leadership, requiring active involvement from microarchitecture definition through RTL development and into back-end implementation and silicon bring-up., * Architecture & Hands-On Design * Define microarchitecture for complex digital blocks and subsystems * Actively contribute to RTL development for key components * Drive design tradeoffs across performance, power, area (PPA), and testability * RTL Development & Integration * Write, review, and integrate high-quality RTL * Lead block- and chip-level integration, resolving interface and system issues * Ensure designs are clean for lint, CDC/RDC, and synthesis * Back-End & Implementation Ownership * Ensure RTL is optimized for synthesis, timing, and physical design * Work on scan insertion, test architecture, and coverage closure * Perform, review and debug logic equivalence checking (LEC) results between RTL and netlists * Define and validate timing constraints (SDC) and complete timing closure * Drive and implement timing and functional ECOs as needed * Design Quality & Signoff * Drive signoff readiness including lint, CDC/RDC, synthesis, LEC, and timing checks * Ensure designs meet functional, timing, power, and test requirements * Support silicon bring-up, debug, and root-cause analysis * Cross-Functional Collaboration * Work closely with verification, physical design, DFT, and firmware teams * Align design decisions with verification plans and implementation Constraints * Act as the technical bridge between front-end and back-end teams ## Related Videos - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Developing the Backend with Stefan Lingler, CTO at Shpock](https://www.wearedevelopers.com/videos/100360-developing-the-backend-with-stefan-lingler-cto-at-shpock) - [Playing Pong on a shoulder press machine](https://www.wearedevelopers.com/videos/100140-playing-pong-on-a-shoulder-press-machine) - [Mutation Testing and Fuzzing in C#](https://www.wearedevelopers.com/videos/703-mutation-testing-and-fuzzing-in-c) - [Nest.js - TypeScript in the backend can also be clean](https://www.wearedevelopers.com/videos/1033-nest-js-typescript-in-the-backend-can-also-be-clean) - [Agent Smith Gets Hardware: Autonomous IoT Hacking From Debug Port to Cloud API](https://www.wearedevelopers.com/videos/100258-agent-smith-gets-hardware-autonomous-iot-hacking-from-debug-port-to-cloud-api) ## Related Articles - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline) - [Fully Remote Software Engineer Jobs](https://www.wearedevelopers.com/magazine/447-fully-remote-software-engineer-jobs) - [Why Attend a Developer Event in 2026?](https://www.wearedevelopers.com/magazine/688-why-attend-a-developer-event-in-2026) - [Where To Find Software Engineering Jobs](https://www.wearedevelopers.com/magazine/396-where-to-find-software-engineering-jobs) - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers) - [Should senior developers refuse interview coding challenges?](https://www.wearedevelopers.com/magazine/29-should-senior-developers-refuse-interview-coding-challenges)