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# Senior/Staff FPGA & Electrical Engineer

- **Company:** BioTalent
- **Location:** San Diego, CA, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Testing (Software), Altium Designer, Computer Engineering, Comsol Multiphysics, Software Debugging, Digital Technology, Embedded C, Fault Tolerance, Firmware, Failure Mode Effects Analysis, Field-Programmable Gate Array (FPGA), Hardware Description Language, Hardware Design, Serial Communications, SystemVerilog, VHSIC Hardware Description Language (VHDL), Hfss, Fpga Hardware, Front End Software Development
- **Published:** November 4, 2026
- **Apply:** https://www.juju.com/job/2_171588337

## About the Role

* BS in Electrical Engineering, Computer Engineering, or related field
 * 8+ years in mixed-signal hardware design for miniaturized, high-reliability electronic systems
 * 5+ years of hands-on FPGA development on low-power families, including timing closure, clock-domain crossing, and simulation-based verification
 * Serial interface design experience on low-power, resource-constrained systems: LVDS signaling, framing and error detection, SPI/I2C, register maps
 * Design of safety-relevant or fault-tolerant digital systems
 * Hands-on inductive power transfer or resonant/magnetics design
 * High-density PCB and flex design in Altium; SPICE and signal-integrity analysis xrbllit
 * Ability to read, debug, and review embedded C firmware
 * Experience taking electronic subsystems from prototype through design verification into production

Nice to Have

 * Active implantable device experience (neurostimulators, cochlear implants, cardiac rhythm devices)
 * Custom silicon co-design and FPGA emulation of partner RTL
 * Functional safety standards (IEC 60601-1 PEMS, IEC 61508, ISO 26262, DO-254)
 * Implantable or body-worn antenna/RF design with EM simulation (HFSS, CST, COMSOL)
 * Coil design and EM/thermal modeling, including MRI compatibility
 * Low-noise neural or bioelectric front-end design
 * Experience supporting IDE, PMA, or 510(k) submissions

## Description

* Architect and develop synthesizable HDL (VHDL or SystemVerilog) for a low-power FPGA serving as the implant's health, status, control, and communications controller
 * Implement supervisory functions: power sequencing, voltage/current/temperature monitoring, watchdogs, fault detection, and safe-state transitions
 * Define and implement the implant side of a low-power serial link to distributed sensing electronics, proven in FPGA emulation with silicon partners ahead of hardware
 * Design fault-tolerant control and monitoring logic, including redundant monitors, independent shutdown paths, and fail-safe defaults; lead FMEA and fault-tree analysis per ISO 14971
 * Own the implant's electrical architecture, including custom silicon integration, inductive charging, RF telemetry, and power budgeting
 * Lead miniaturized PCB and flex-rigid design in Altium
 * Define and execute electrical and FPGA verification plans within design controls (IEC 60601-1, IEC 62304, ISO 14708)
 * Review and debug firmware and test software alongside the firmware team; support design transfer to contract manufacturers