> Markdown version of [/jobs/ext/4564614-sr-applications-engineer](https://www.wearedevelopers.com/jobs/ext/4564614-sr-applications-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Sr. Applications Engineer - **Company:** Achronix Semiconductor Corporation - **Location:** Santa Clara, CA, United States - **Experience:** Expert - **Contract:** Permanent contract - **Skills:** Application Notes, Software Applications, Systems Engineering, Logic Synthesis of Circuits, Field-Programmable Gate Array (FPGA), PCI Express, Static Timing Analysis, SystemVerilog, Verilog - **Published:** November 4, 2026 - **Apply:** https://www.juju.com/job/7_ED3BF1E001F5F247E1F92D569621E6E3 ## About the Role If you're a systems-level thinker who thrives on solving gnarly design challenges at a fast pace, collaborating with software and hardware engineers, and helping world-class customers push programmable silicon to the limits -this is your next big move. Report directly to the VP, Software & Applications Engineering!Job Description/ResponsibilitiesProvide support to customers worldwide, to resolve challenging technical issues and ensure successful integration of Achronix programmable logic solutions.Create reference/demo designs, other technical collateral like user guides and application notes to showcase and document FPGA features to customers.Work closely with engineering teams to drive product planning and implementation efforts.Work with Applications and System Engineering teams for FPGA bring-up, validation, and troubleshooting system-level tools.Provide on-site support to customers as needed, for issues ranging from software set-up to benchmarking and silicon characterization.Required SkillsStrong problem solving skills - this is a prerequisite to be successful in this positionFamiliarity with Verilog, System Verilog and VHDLStrong logic design and verification backgroundGood communication and writing skills with ability to multi-taskKnowledge of timing constraints and Static timing analysisUnderstanding of FPGA/programmable logic architecture and design flowsSome experience with memory interfaces such as DDR4Some experience with SerDes and protocol IP such as PCIe, Interlaken, and 10G/40G/100G/400G EthernetEducation and ExperienceBachelor's or Master's degree in EE, CE or equivalent work experienceOne to five years experience working with FPGAs and/or ASICs in an applications, system-level, design, or verification roleAbility to work in the lab with test equipment (oscilloscopes, function generators, logic analyzers, etc.) is a plus.