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# RTL Design Engineer

- **Company:** Wipro Limited
- **Location:** Mountain View, CA, United States
- **Experience:** Experienced
- **Salary:** $80,000 - $160,000
- **Contract:** Internship / Graduate position
- **Skills:** Computer Engineering, Microarchitecture, Data Transport Utility, Software Debugging, Logic Synthesis of Circuits, SystemVerilog, Verilog, Application Specific Integrated Circuits, Information Technology, Physical Design
- **Published:** November 4, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=e218dea774d19771

## About the Role

* 9+ years of related technical engineering experience
 * OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience
 * OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
 * 8+ years of experience delivering successful IP or Application Specific Integrated Circuits (ASIC)/SOC designs related to arbitration and fabric logics for high-throughput/low-latency data transport.
 * 8+ years expertise in Digital Design including RTL coding in Verilog/System Verilog, RTL2PD tool/flow setup/maintenance/debug: Lint/CDC/RDC/VCLP/Synthesis/Timing constraints/FEV

Additional Or Preferred Qualifications

 * 15+ years technical engineering experience
 * OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience
 * OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
 * OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience.
 * Track record of successful ASIC tape outs in deep sub-micron technologies
 * Deep understanding of the physical design impact for each micro-architecture and work closely with PD engineers to find the best tradeoff given the performance/area/power constraints.
 * Experienced on a variety of micro-architecture areas such as Complex Control Paths, Memory hierarchies and standard industry interfaces such as Advanced extensible Interface (AXI).
 * 5+ years of experience in designing complex control logics on Network-On-Chip ASICs
 * Excellent communication skills and ability to facilitate collaboration.

Mandatory Skills: RTL coding .

Experience: 5-8 Years .