> Markdown version of [/jobs/ext/4565852-sr-solutions-engineer-fpga-pcie](https://www.wearedevelopers.com/jobs/ext/4565852-sr-solutions-engineer-fpga-pcie). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Sr Solutions Engineer-FPGA/PCIe - **Company:** Advanced Micro Devices, Inc. - **Location:** San Jose, CA, United States - **Experience:** Expert - **Contract:** Permanent contract - **Skills:** Computer Engineering, Software Debugging, Logic Synthesis of Circuits, Embedded Software, Emulators, Ethernet, Firmware, Field-Programmable Gate Array (FPGA), Make (Software), Python (Programming Language), PCI Express, Shell Script, SystemVerilog, Systems Integration, Tcl (Programming Language), Verilog, Vivado, Application Specific Integrated Circuits, Hardware Debugging - **Published:** November 4, 2026 - **Apply:** https://www.juju.com/job/7_ECB350772EEB6BA8DAEF1083AFA3E9B4 ## About the Role You are passionate about modern processor architecture, digital design, and system-level validation. You thrive in collaborative environments, communicate effectively across global teams, and bring strong analytical and problem-solving skills. You are eager to learn and tackle complex technical challenges. KEY RESPONSIBILITIES: Participate in technical role in all phases of the product development cycle from new product exploration, architecture through implementation, prototyping, validation, productization and support including but not limited to architecture, design, and documentation for Ips Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be developed RTL Development: Design, verify, and validate high-performance logic using System Verilog/Verilog. You will focus on the data and control path, implementing deigns for PCIe (Gen 6/7), CXL, UAL, Ethernet, and DDR5/6. System Level Integration: Utilize the standard ASIC flows , AMD (Xilinx) Vivado ecosystems to integrate custom IP with other subsystemsPre-Si Verification: Perform pre-silicon verification and emulation to ensure functional correctness and performance Post-Si Validation: Lead the "Bring-up" process in the lab. Perform post-silicon validation, debugging complex interactions between the embedded software and hardware fabric PREFERRED EXPERIENCE: Hands-on experience with ASIC/FPGAs RTL Expertise: Expert in SystemVerilog/Verilog, synchronous design, and timing closure for high-speed logic Protocols: Knowledge of PCIe, AXI, DDR, and Ethernet. Familiarity with CXL or UAL is highly desirable Verification: Familiarity with UVM-based verification frameworks and emulation platforms (Palladium, Protium, Zebu) Validation: Experience in hardware debugging Tools: Proficiency in Python, Tcl, Makefiles, and Shell scripting for automation ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering