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# Field-Programmable Gate Arrays Engineer

- **Company:** The Technical
- **Location:** Boulder, CO, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** C++ (Programming Language), Computer Engineering, Data Recovery, Software Debugging, Embedded Software, Field-Programmable Gate Array (FPGA), System on a Chip, SystemVerilog, Git Flow
- **Published:** November 4, 2026
- **Apply:** https://www.juju.com/job/2_171578448

## About the Role

Required

 * B.S. in Electrical Engineering, Computer Engineering, or a closely related field; M.S. preferred

 * 7+ years of professional FPGA design experience, with a track record of owning a subsystem end to end

 * Experience with SystemVerilog

 * Hands-on experience designing and debugging high-speed serial transceivers (SerDes, multi-gigabit links, clock/data recovery, equalization, jitter and eye-diagram work)

 * Practical DDR4 experience: controller integration, calibration, timing closure, and real-world throughput debugging

 * Strong lab and debug skills

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 * Self-directed and independent with a willingness to learn on the go

Nice to Have

 * Experience with Intel/Altera FPGAs, particularly Arria 10

 * Experience with Efinix FPGAs (Trion T20)

 * DSP and control-systems background - digital filters, feedback loops, closed-loop sensor control

 * C++ and System-on-Chip development, including Arria 10 HPS or similar hard-processor integration

 * Experience in a regulated medical device environment (ISO 13485, IEC 62304, design controls, V&V documentation)

 * Familiarity with Git-based workflows

## Description

We are looking for a Senior FPGA Engineer to advance our existing FPGA architecture, help design the next-generation system, design, verify, and implement new features for our platform. You will own FPGA subsystems end to end - from architecture through verification - working at the hardware/software boundary to keep our systems fast, stable, and reliable.

WHAT YOU'LL DO

 * Architect, implement, and verify FPGA designs for our scan system

 * Design and implement high-speed serial transceiver links between scan chassis

 * Design and incorporate DDR4 memory on the System on Module

 * Improve existing real-time control and DSP data paths (filtering, decimation, feedback loops) that keep the sensor array stable

 * Drive timing closure, resource budgeting, and design-for-test across Arria 10 devices

 * Build simulation and verification environments

 * Partner with embedded software on the hardware/software boundary, register maps, DMA, and SoC integration

 * Contribute to design documentation and verification evidence within our ISO 13485 design control process

 * Participate in on-site testing and measurements using the HEDscan system