> Markdown version of [/jobs/ext/4577772-pd-methodology-engineer-annapurna-labs-cloud-scale-machine-learning](https://www.wearedevelopers.com/jobs/ext/4577772-pd-methodology-engineer-annapurna-labs-cloud-scale-machine-learning). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

---

# PD Methodology Engineer, Annapurna Labs - Cloud Scale Machine Learning

- **Company:** Amazon.com, Inc.
- **Location:** Austin, TX, United States
- **Salary:** $176,600 - $247,300
- **Contract:** Permanent contract
- **Skills:** Computer-Aided Design, Amazon Web Services, Cloud Computing, Data Centers, Software Debugging, Perl (Programming Language), Formal Verification, Python (Programming Language), Machine Learning, Performance Tuning, System on a Chip, Tcl (Programming Language), Scripting, Application Specific Integrated Circuits, AWS Trainium, Physical Design
- **Published:** November 5, 2026
- **Apply:** https://www.jobmonkeyjobs.com/career/28162361/Pd-Methodology-Engineer-Annapurna-Labs-Cloud-Scale-Machine-Learning-Texas-Austin-7375

## About the Role

Bachelor's degree in Electrical Engineering or a related field

 - Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills

Preferred Qualifications

 - Master's degree in Electrical or Communications Engineering or a related field
 - Experience with industry standard tools and scripting languages (Python or Perl) for automation

## Description

Custom SoCs (System on Chip) live at the heart of Amazon Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, Trainium Systems (our custom designed machine learning inference and training datacenter servers). Our success depends on our world-class server infrastructure; we're handling massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs., Define, develop and deploy innovative physical design and verification methodologies (RTL2GDS) for ML Accelerator chips in advanced nodes

Drive Optimizations in CAD flows/methodologies for PPA and TAT improvements

Work with EDA tool vendors to evaluate new methods, resolve bugs, improve usability.

Fine tune cloud infrastructure to improve compute and storage utilization for physical design work.

Interface directly with RTL, Physical Design, Package Design, DFT teams to improve methodologies and efficiencies.

Be able to independently troubleshoot digital tool flow usage and deploy solutions;

Fluent in scripting languages such as TCL, Python, etc. and able to build scalable and efficient flows to support parallel design developments

Create Dashboard and Central reports for project tracking and visualizing QoR/stats