> Markdown version of [/jobs/ext/4579944-ai-vision-research-engineer-pico-san-jose](https://www.wearedevelopers.com/jobs/ext/4579944-ai-vision-research-engineer-pico-san-jose). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # AI Vision Research Engineer - PICO - San Jose - **Company:** Beijing ByteDance Technology Co Ltd - **Location:** San Jose, CA, United States - **Experience:** Experienced - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Computer Vision, C++ (Programming Language), Cloud Computing, Programming Tools, Field-Programmable Gate Array (FPGA), Python (Programming Language), MATLAB, Performance Tuning, Tensorflow, Software Engineering, Software Requirements Analysis, Information Technology - **Published:** November 5, 2026 - **Apply:** https://www.careerbuilder.com/job-details/ai-vision-research-engineer-pico-san-jose-san-jose-ca--f34e9365-48d4-4d8c-8457-93a7eb27ae36 ## About the Role Artificial Intelligence (AI), Accounts Receivable, Data Collection, Customer/Consumer Behavior, Algorithms, Scene Understanding, Performance Tuning/Optimization, Artificial Intelligence (AI), Software Design, Cloud Computing, * PhD in the fields of Electrical Engineering, Computer Science, Physics and related technical discipline. * 3 + years of experience in research experience in the fields of ML algorithm or AI accelerator design * 3+ years for experience with programming tools and languages such as C/C++, MATLAB, Python. Preferred Qualification(s): * Familiar with appropriate ML frameworks. * Good communication skills, open minded and enthusiastic about new technologies ## Description * Innovate and develop a power-efficient, low-latency, highly-intelligent machine perception vision system in a VR/AR product. * Develop necessary training, data collection/generation pipeline along with state of art ML algorithm/framework for understanding of the scene and user behaviors. * Map the ML algorithm to the HW accelerator, identify performance bottleneck, optimize performance and efficiency, propose more efficient HW/SW co-design for AI accelerator. * Collaborate with the x-functions team and translate system requirements into a proper cloud-edge workload partition and edge ML accelerator HW/SW requirement. * Perform quantitative evaluations through the use of system modeling, FPGA prototyping for validating ideas and architecture options.Minimum Qualification(s)